From patchwork Fri Jun 10 09:14:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12877097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECA84C43334 for ; Fri, 10 Jun 2022 09:17:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348835AbiFJJRJ (ORCPT ); Fri, 10 Jun 2022 05:17:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344194AbiFJJQO (ORCPT ); Fri, 10 Jun 2022 05:16:14 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A0FE8250692; Fri, 10 Jun 2022 02:15:31 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id E505816A8; Fri, 10 Jun 2022 12:16:10 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com E505816A8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1654852570; bh=HZy3PdUSoh84jD78k5L1zP8v+9AYPA6C/fEw3gH+MnY=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=YzGSQ1/YUViw/G3XFydThK2sMnT5cVSZ2M86ua08gzXIgayFhAKNScxnVskI3srXX 0PvOQ4Viv+Ct2g0JwScb9xPDqjgKtbOqqV1W0l7sOeJTIryoWxMoRStzxYIADCUl6h C6BnwoKuw7DrJukhAMM5MWXJCvBNidTO5pOOyBzY= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 10 Jun 2022 12:15:18 +0300 From: Serge Semin To: Gustavo Pimentel , Vinod Koul , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Frank Li , Manivannan Sadhasivam CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , =?utf-8?q?Krzys?= =?utf-8?q?ztof_Wilczy=C5=84ski?= , , , Subject: [PATCH v3 20/24] dmaengine: dw-edma: Drop DT-region allocation Date: Fri, 10 Jun 2022 12:14:55 +0300 Message-ID: <20220610091459.17612-21-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220610091459.17612-1-Sergey.Semin@baikalelectronics.ru> References: <20220610091459.17612-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There is no point in allocating an additional memory for the data target regions passed then to the client drivers. Just use the already available structures defined in the dw_edma_chip instance. Note these regions are unused in normal circumstances since they are specific to the case of eDMA being embedded into the DW PCIe End-point and having it's CSRs accessible over a End-point' BAR. This case is only known to be implemented as a part of the Synopsys PCIe EndPoint IP prototype kit. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- drivers/dma/dw-edma/dw-edma-core.c | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 7ba3b60c960c..98a94a66fb82 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -744,7 +744,6 @@ static void dw_edma_free_chan_resources(struct dma_chan *dchan) static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc) { struct dw_edma_chip *chip = dw->chip; - struct dw_edma_region *dt_region; struct device *dev = chip->dev; struct dw_edma_chan *chan; struct dw_edma_irq *irq; @@ -760,12 +759,6 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc) for (i = 0; i < ch_cnt; i++) { chan = &dw->chan[i]; - dt_region = devm_kzalloc(dev, sizeof(*dt_region), GFP_KERNEL); - if (!dt_region) - return -ENOMEM; - - chan->vc.chan.private = dt_region; - chan->dw = dw; if (i < dw->wr_ch_cnt) { @@ -813,17 +806,11 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc) chan->msi.data); chan->vc.desc_free = vchan_free_desc; - vchan_init(&chan->vc, dma); + chan->vc.chan.private = chan->dir == EDMA_DIR_WRITE ? + &dw->chip->dt_region_wr[chan->id] : + &dw->chip->dt_region_rd[chan->id]; - if (chan->dir == EDMA_DIR_WRITE) { - dt_region->paddr = chip->dt_region_wr[chan->id].paddr; - dt_region->vaddr = chip->dt_region_wr[chan->id].vaddr; - dt_region->sz = chip->dt_region_wr[chan->id].sz; - } else { - dt_region->paddr = chip->dt_region_rd[chan->id].paddr; - dt_region->vaddr = chip->dt_region_rd[chan->id].vaddr; - dt_region->sz = chip->dt_region_rd[chan->id].sz; - } + vchan_init(&chan->vc, dma); dw_edma_v0_core_device_config(chan); }