From patchwork Fri Jun 10 20:22:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12878075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28A0AC433EF for ; Fri, 10 Jun 2022 20:23:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350444AbiFJUXp (ORCPT ); Fri, 10 Jun 2022 16:23:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350639AbiFJUXL (ORCPT ); Fri, 10 Jun 2022 16:23:11 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8081B2FFAAE; Fri, 10 Jun 2022 13:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654892590; x=1686428590; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NbhYVfdyvwM1DkmCBeU6JeKZEr+9LdD5PAXZvAOfIEo=; b=dDi+Yiv2vsuvO77UznwC2pO5IXdbnTKdgM5SDTyyqHoR53Ms/bGYYNYO VPhveYVUxcH/qx13jBb/EfqCgpJVeEYxo5JNqqlEaCIW+sfkmvukTaIrx ULf7aXMejUV2jMi7uL01JIUij0utzr5VtWt45t/Av9tZLIB7e1PnJZWe/ uJ3brQWUAHbCcSuFEEiVDLVpulDin/6a6CLVigMp7t0Bt0iVdafdnkPI4 wXJvOMEDd+F5TLcmDPeN5WQ6oLf+AD/cJwkxjHSzwxkbtfz5TT9l7wXhx Kg2EAUGE59lkN8nmX34/pcm4Q4a+OaDxZK6JuBZsVr9E/9nfjTR8Fsv51 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10374"; a="341795777" X-IronPort-AV: E=Sophos;i="5.91,291,1647327600"; d="scan'208";a="341795777" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2022 13:23:09 -0700 X-IronPort-AV: E=Sophos;i="5.91,291,1647327600"; d="scan'208";a="534218605" Received: from pleung-mobl1.amr.corp.intel.com (HELO localhost) ([10.212.33.34]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2022 13:23:08 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Ira Weiny , Alison Schofield , Vishal Verma , Dave Jiang , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V11 6/8] cxl/port: Introduce cxl_cdat_valid() Date: Fri, 10 Jun 2022 13:22:57 -0700 Message-Id: <20220610202259.3544623-7-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220610202259.3544623-1-ira.weiny@intel.com> References: <20220610202259.3544623-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ira Weiny The CDAT data is protected by a checksum and should be the proper length. Introduce cxl_cdat_valid() to validate the data. While at it check and store the sequence number. Signed-off-by: Ira Weiny --- Changes from V8 Move code to cxl/core/pci.c Changes from V6 Change name to cxl_cdat_valid() as this validates all the CDAT data not just the header Add error and debug prints Changes from V5 New patch, split out Update cdat_hdr_valid() Remove revision and cs field parsing There is no point in these Add seq check and debug print. --- drivers/cxl/cdat.h | 2 ++ drivers/cxl/core/pci.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h index c6a48ab326bf..39eb561081f2 100644 --- a/drivers/cxl/cdat.h +++ b/drivers/cxl/cdat.h @@ -91,10 +91,12 @@ * * @table: cache of CDAT table * @length: length of cached CDAT table + * @seq: Last read Sequence number of the CDAT table */ struct cxl_cdat { void *table; size_t length; + u32 seq; }; #endif /* !__CXL_CDAT_H__ */ diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 84dc82f7dff0..cb70287e2984 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -531,6 +531,40 @@ static int cxl_cdat_get_length(struct device *dev, return rc; } +static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat) +{ + u32 *table = cdat->table; + u8 *data8 = cdat->table; + u32 length, seq; + u8 check; + int i; + + length = FIELD_GET(CDAT_HEADER_DW0_LENGTH, table[0]); + if ((length < CDAT_HEADER_LENGTH_BYTES) || (length > cdat->length)) { + dev_err(dev, "CDAT Invalid length %u (%zu-%zu)\n", length, + CDAT_HEADER_LENGTH_BYTES, cdat->length); + return false; + } + + for (check = 0, i = 0; i < length; i++) + check += data8[i]; + + dev_dbg(dev, "CDAT length %u CS %u\n", length, check); + if (check != 0) { + dev_err(dev, "CDAT Invalid checksum %u\n", check); + return false; + } + + seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]); + /* Store the sequence for now. */ + if (cdat->seq != seq) { + dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq); + cdat->seq = seq; + } + + return true; +} + static int cxl_cdat_read_table(struct device *dev, struct pci_doe_mb *cdat_mb, struct cxl_cdat *cdat) @@ -578,6 +612,8 @@ static int cxl_cdat_read_table(struct device *dev, } while (entry_handle != CXL_DOE_TABLE_ACCESS_LAST_ENTRY); + if (!rc && !cxl_cdat_valid(dev, cdat)) + return -EIO; return rc; }