| Message ID | 20220822184701.25246-13-Sergey.Semin@baikalelectronics.ru (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: dwc: Add generic resources and Baikal-T1 support | expand |
On Mon, 22 Aug 2022 21:46:53 +0300, Serge Semin wrote: > DW PCIe EP/RP AXI- and TRGT1-master interfaces are responsible for the > application memory access. They are used by the RP/EP PCIe buses (MWr/MWr > TLPs emitted by the peripheral PCIe devices) and the eDMA block. Since all > of them mainly involve the system memory and basically mean DMA we can > expect the corresponding platforms can be designed in a way to make sure > the transactions are cache-coherent. As such the DW PCIe DT-nodes can have > the 'dma-coherent' property specified. Let's permit it in the DT-bindings > then. > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > > --- > > Changelog v3: > - This is a new patch created on v3 lap of the series. > --- > Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml index 4fa027e6fd99..188e708f375d 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml @@ -164,6 +164,8 @@ properties: configuration space registers, Port Logic registers, DMA and iATU registers. This feature has been available since DWC PCIe v4.80a. + dma-coherent: true + additionalProperties: true definitions:
DW PCIe EP/RP AXI- and TRGT1-master interfaces are responsible for the application memory access. They are used by the RP/EP PCIe buses (MWr/MWr TLPs emitted by the peripheral PCIe devices) and the eDMA block. Since all of them mainly involve the system memory and basically mean DMA we can expect the corresponding platforms can be designed in a way to make sure the transactions are cache-coherent. As such the DW PCIe DT-nodes can have the 'dma-coherent' property specified. Let's permit it in the DT-bindings then. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- Changelog v3: - This is a new patch created on v3 lap of the series. --- Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml | 2 ++ 1 file changed, 2 insertions(+)