From patchwork Mon Sep 5 19:23:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12966466 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E5F0ECAAD3 for ; Mon, 5 Sep 2022 19:25:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230047AbiIETZR (ORCPT ); Mon, 5 Sep 2022 15:25:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229738AbiIETZR (ORCPT ); Mon, 5 Sep 2022 15:25:17 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 981F11D300; Mon, 5 Sep 2022 12:25:15 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 36C9861464; Mon, 5 Sep 2022 19:25:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 72B9FC4347C; Mon, 5 Sep 2022 19:25:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662405914; bh=falzg4hl4/KX290uSBifmOXJSnweYuOhtmxMd5uXnF0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VJ6TFJjGpyTfdZvcTp12RgL9G1yzer1PD1IZ5Gn38LBgZps/0giuJ84MPEt84qtrL JOpSvLLKOhsrCp7oJ1ocUIaraBEhOpX/A7K9DdFo6Onif/lZuKEt6JO6Xms2YnlHK/ tIeYL4Eotsl7RWTxPhmwXA/a6nWLAJayyCiveNO03jFT8GyjeZ9cGgOgXf1vnQ+Kqg F8sdcEg9IPcIjiQxsVAYRxIMg7yANuzQqt80hLX86IPYZJksLVi+LGvjF6u6xOrQn/ vJN0fSQlqsdA0hLvALLDN7lXlcYVV6M3Bq5QH/65+ft+QjyZqqVSRqgKFlYJtvGKJ1 uf7ttbzqnGXmg== Received: by pali.im (Postfix) id 0D0A42B22; Mon, 5 Sep 2022 21:25:14 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Thomas Petazzoni , Mauri Sandberg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/7] dt-bindings: PCI: mvebu: Add orion5x compatible Date: Mon, 5 Sep 2022 21:23:06 +0200 Message-Id: <20220905192310.22786-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220905192310.22786-1-pali@kernel.org> References: <20220718202843.6766-1-maukka@ext.kapsi.fi> <20220905192310.22786-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Mauri Sandberg Add a compatible string to bindings to indicate that orion5x PCIe is supported too. Orion requires additional bindings for config space registers. Signed-off-by: Mauri Sandberg Signed-off-by: Pali Rohár Acked-by: Rob Herring --- Changes in v3: * Add more detailed information about MMIO registers --- Documentation/devicetree/bindings/pci/mvebu-pci.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt index 8f0bca42113f..d8d6afc6376a 100644 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -7,6 +7,7 @@ Mandatory properties: marvell,armada-xp-pcie marvell,dove-pcie marvell,kirkwood-pcie + marvell,orion5x-pcie - #address-cells, set to <3> - #size-cells, set to <2> - #interrupt-cells, set to <1> @@ -60,7 +61,8 @@ PCIe interface, having the following mandatory properties: - reg: used only for interrupt mapping, so only the first four bytes are used to refer to the correct bus number and device number. - assigned-addresses: reference to the MMIO registers used to control - this PCIe interface. + this PCIe interface. first value controls internal registers and + second value (Orion-specific) controls config space registers. - clocks: the clock associated to this PCIe interface - marvell,pcie-port: the physical PCIe port number - status: either "disabled" or "okay"