From patchwork Tue Sep 6 12:44:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baolu Lu X-Patchwork-Id: 12967448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ED0BECAAA1 for ; Tue, 6 Sep 2022 12:51:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240228AbiIFMvd (ORCPT ); Tue, 6 Sep 2022 08:51:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239159AbiIFMvT (ORCPT ); Tue, 6 Sep 2022 08:51:19 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E8D362AB1; Tue, 6 Sep 2022 05:51:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662468673; x=1694004673; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+5c5bAJ7aQCZq6Sk3d3o9QvKpOswZjv+bhsb4GOFLxg=; b=Fxi0Sv0NP5fhUOIQuZ7vYS1gx1ZrTf3tA9V5cR2/xWiWHjsIhzReJpcJ cbngXt8vEp3dcazPByUbj0OcKhvo5JXWO42W7V4Vc4DPaN2wwsWLJ3lIS ECu5tD0v2DvjYQpN3eDkl+r7Ah/XukzWXMr0GNR7XQjWXIHNW2bibY9r9 AFwXZs4ACW3uqN1HKFv8Y2Vyfne7jgAjgz4wrwhmERIt6oUKon0ffJpwV t7QLNpuAd75Qql0oIdEDExj9Tbccs6vJnjm8CM9mbRctfNjzXZVTeXxXa AaZPKCCTciNoAufA5VzqKZjuSLTX+OPZNE/mFwbOOODy/IzpACIK2Zpy8 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10462"; a="322757320" X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="322757320" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2022 05:51:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="591252889" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga006.jf.intel.com with ESMTP; 06 Sep 2022 05:51:08 -0700 From: Lu Baolu To: Joerg Roedel , Jason Gunthorpe , Christoph Hellwig , Bjorn Helgaas , Kevin Tian , Ashok Raj , Will Deacon , Robin Murphy , Jean-Philippe Brucker , Dave Jiang , Fenghua Yu , Vinod Koul Cc: Eric Auger , Liu Yi L , Jacob jun Pan , Zhangfei Gao , Zhu Tony , iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v13 04/13] PCI: Enable PASID only when ACS RR & UF enabled on upstream path Date: Tue, 6 Sep 2022 20:44:49 +0800 Message-Id: <20220906124458.46461-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906124458.46461-1-baolu.lu@linux.intel.com> References: <20220906124458.46461-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Requester ID/Process Address Space ID (PASID) combination identifies an address space distinct from the PCI bus address space, e.g., an address space defined by an IOMMU. But the PCIe fabric routes Memory Requests based on the TLP address, ignoring any PASID (PCIe r6.0, sec 2.2.10.4), so a TLP with PASID that SHOULD go upstream to the IOMMU may instead be routed as a P2P Request if its address falls in a bridge window. To ensure that all Memory Requests with PASID are routed upstream, only enable PASID if ACS P2P Request Redirect and Upstream Forwarding are enabled for the path leading to the device. Suggested-by: Jason Gunthorpe Suggested-by: Kevin Tian Signed-off-by: Lu Baolu Acked-by: Bjorn Helgaas Reviewed-by: Jason Gunthorpe Tested-by: Tony Zhu --- drivers/pci/ats.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index c967ad6e2626..f9cc2e10b676 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -382,6 +382,9 @@ int pci_enable_pasid(struct pci_dev *pdev, int features) if (!pasid) return -EINVAL; + if (!pci_acs_path_enabled(pdev, NULL, PCI_ACS_RR | PCI_ACS_UF)) + return -EINVAL; + pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported); supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;