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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2022 19:28:26.4711 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee1c7464-b0e0-4e90-cb8a-08daa319f2a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6535 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to configure a slot as a pluggable slot by not power-gating the respective controller based on the DT property "hotplug-gpios". Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-tegra194.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 2600304522eb..0370e881422d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -280,6 +280,8 @@ struct tegra_pcie_dw { unsigned int phy_count; struct phy **phys; + bool slot_pluggable; + struct dentry *debugfs; /* Endpoint mode specific */ @@ -1089,6 +1091,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) { struct platform_device *pdev = to_platform_device(pcie->dev); struct device_node *np = pcie->dev->of_node; + struct property *prop; int ret; pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); @@ -1158,6 +1161,10 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) pcie->enable_srns = of_property_read_bool(np, "nvidia,enable-srns"); + prop = of_find_property(np, "hotplug-gpios", NULL); + if (prop) + pcie->slot_pluggable = true; + if (pcie->of_data->mode == DW_PCIE_RC_TYPE) return 0; @@ -1655,7 +1662,7 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) } pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); - if (!pcie->link_state) { + if (!pcie->link_state && !pcie->slot_pluggable) { ret = -ENOMEDIUM; goto fail_host_init; } @@ -2267,7 +2274,7 @@ static int tegra_pcie_dw_remove(struct platform_device *pdev) struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return 0; debugfs_remove_recursive(pcie->debugfs); @@ -2296,7 +2303,7 @@ static int tegra_pcie_dw_suspend_late(struct device *dev) return -EPERM; } - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return 0; /* Enable HW_HOT_RST mode */ @@ -2315,7 +2322,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) { struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return 0; tegra_pcie_downstream_dev_to_D0(pcie); @@ -2330,7 +2337,7 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev) struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); int ret; - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return 0; ret = tegra_pcie_config_controller(pcie, true); @@ -2366,7 +2373,7 @@ static int tegra_pcie_dw_resume_early(struct device *dev) return -ENOTSUPP; } - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return 0; /* Disable HW_HOT_RST mode */ @@ -2388,7 +2395,7 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev) struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return; debugfs_remove_recursive(pcie->debugfs);