From patchwork Wed Nov 9 08:25:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13037247 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C0C0C4332F for ; Wed, 9 Nov 2022 08:26:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229797AbiKII0e (ORCPT ); Wed, 9 Nov 2022 03:26:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229814AbiKII0d (ORCPT ); Wed, 9 Nov 2022 03:26:33 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3A1E13D52 for ; Wed, 9 Nov 2022 00:26:32 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A98QK11114296; Wed, 9 Nov 2022 02:26:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667982380; bh=hlEm72WqMoZKFSWrfJiaow4wqktKLw+YOG3Ivwy4ACE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uLI6is7rKQq7CjSfxfXpLNQRvjiAgDQZmBOqbOVak7iiZbeWQmvXjgzc4WAR/B8MS tlSlYWWotXPAH+n55FqmMFQFGbmbuDpYV+D8213y62QbR4RyEoc1f1UrO9N8eTKJBd 72z85knjLGz/qtBKcqyIVdAuhA4yNsqvG53sIfsk= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A98QK82039242 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Nov 2022 02:26:20 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 9 Nov 2022 02:26:20 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 9 Nov 2022 02:26:20 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A98QHlX039434; Wed, 9 Nov 2022 02:26:18 -0600 From: Matt Ranostay To: , , , , CC: , , Matt Ranostay Subject: [PATCH v5 4/4] PCI: j721e: Add warnings on num-lanes misconfiguration Date: Wed, 9 Nov 2022 00:25:56 -0800 Message-ID: <20221109082556.29265-5-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221109082556.29265-1-mranostay@ti.com> References: <20221109082556.29265-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Added dev_warn messages to alert of misconfigurations for incorrect number of lanes setting, or the lack of one being defined. Signed-off-by: Matt Ranostay Reviewed-by: Vignesh Raghavendra --- drivers/pci/controller/cadence/pci-j721e.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 83b8100afaff..f6320ad75587 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -465,9 +465,16 @@ static int j721e_pcie_probe(struct platform_device *pdev) pcie->user_cfg_base = base; ret = of_property_read_u32(node, "num-lanes", &num_lanes); - if (ret || num_lanes > data->max_lanes) + if (ret) { + dev_warn(dev, "no num-lanes defined, defaulting to 1\n"); num_lanes = 1; + } + if (num_lanes > data->max_lanes) { + dev_warn(dev, "defined num-lanes %u is greater than the allowed maximum of %u, defaulting to 1\n", + num_lanes, data->max_lanes); + num_lanes = 1; + } pcie->max_lanes = data->max_lanes; pcie->num_lanes = num_lanes;