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linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Shradha Todi Subject: [PATCH 1/6] dt-bindings: phy: Add PCIe PHY bindings for FSD Date: Mon, 21 Nov 2022 16:22:05 +0530 Message-Id: <20221121105210.68596-2-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221121105210.68596-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VTe0xTVxjf6X30gqne8BgH5lhznVlgAemE7vDSRZl2c1nINEycE7v2piCl rb3Fx4gCii5rBHmqcaUjFsPADZUCltfKa1AQHI6OkGkQCFtgw+E6rJs8tkLL9t/vfN/v9/2+ 7zvnUJjPMBlEpal0rFYlVTKkN97YFRISNinLkkXUmjei9rkOHI0bG0m0VNzDR53mBj4amRni o8ozqWjY+jr6svsegc6abpJo6OcLJCqYnsBQzoUFAg03G0g0aOwlUWGNE0d5i3k4an9SA9BU 6SSBvru9F11rmOejq0MWAp1r6+Yjo6UcoPyuU+jBbC2Bmh7asLeCJAvPi4Gkoi5TUlfzOSl5 ONJKSqbsl3kSa/nXfIm5MltSUF8DJL2jd3iSP+uCE70PpMelslI5qxWyKplanqZSxDN79qbs TIkSR4jCRNHoTUaokmaw8UzCe4lhu9KUrsEZ4TGpMtMVSpRyHLNlW5xWnaljhalqThfPsBq5 UhOpCeekGVymShGuYnUxooiIN6JcxMPpqcu5I4SmzPeE7XErLwf0rtcDLwrSkfDHpp/4euBN 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20221121104719epcas5p2f87febfba74a4ca6807b3095acf507d0 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221121104719epcas5p2f87febfba74a4ca6807b3095acf507d0 References: <20221121105210.68596-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document the PCIe PHY device tree bindings for Tesla FSD SoC Signed-off-by: Shradha Todi --- .../bindings/phy/phy-tesla-pcie.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml b/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml new file mode 100644 index 000000000000..8fa9a050af7a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-tesla-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD SoC PCIe PHY + +maintainers: + - Shradha Todi + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - tesla,fsd-pcie-phy + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + minItems: 2 + maxItems: 2 + items: + enum: [phy, pcs] + description: | + phy is the register access to PMA layer + pcs is the register access to PCS layer + + phy-mode: + description: | + Defines the bifurcation mode of the PHY + + tesla,pmureg-phandle: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for PMU system controller interface used to + control PMU register bits for PCIe PHY + + tesla,pcie-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for system control registers, used to + control phy signals at system level + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - phy-mode + - tesla,pmureg-phandle + - tesla,pcie-sysreg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie_phy0: pcie-phy@15080000 { + compatible = "tesla,fsd-pcie-phy"; + #phy-cells = <0>; + reg = <0x0 0x15080000 0x0 0x2000>, <0x0 0x150A0000 0x0 0x1000>; + reg-names = "phy", "pcs"; + tesla,pmureg-phandle = <&pmu_system_controller>; + tesla,pcie-sysreg = <&sysreg_fsys0>; + phy-mode = <0>; + status = "disabled"; + }; + }; +...