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Thu, 12 Jan 2023 19:44:52 +0000 From: Frank Li To: Minghuan Lian , Mingkai Hu , Roy Zang , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , linuxppc-dev@lists.ozlabs.org (open list:PCI DRIVER FOR FREESCALE LAYERSCAPE), linux-pci@vger.kernel.org (open list:PCI DRIVER FOR FREESCALE LAYERSCAPE), linux-arm-kernel@lists.infradead.org (moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE), linux-kernel@vger.kernel.org (open list) Cc: imx@lists.linux.dev Subject: [PATCH 1/1] PCI: layerscape: Add the workaround for A-010305 Date: Thu, 12 Jan 2023 14:44:33 -0500 Message-Id: <20230112194433.1514149-1-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: SJ0PR05CA0194.namprd05.prod.outlook.com (2603:10b6:a03:330::19) To HE1PR0401MB2331.eurprd04.prod.outlook.com (2603:10a6:3:24::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: HE1PR0401MB2331:EE_|AM9PR04MB8178:EE_ X-MS-Office365-Filtering-Correlation-Id: a3c4e41c-a885-42d4-f97d-08daf4d578ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Signed-off-by: Frank Li --- .../pci/controller/dwc/pci-layerscape-ep.c | 112 +++++++++++++++++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index ed5cfc9408d9..1b884854c18e 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -18,6 +18,22 @@ #include "pcie-designware.h" +#define PCIE_LINK_CAP 0x7C /* PCIe Link Capabilities*/ +#define MAX_LINK_SP_MASK 0x0F +#define MAX_LINK_W_MASK 0x3F +#define MAX_LINK_W_SHIFT 4 + +/* PEX PFa PCIE pme and message interrupt registers*/ +#define PEX_PF0_PME_MES_DR 0xC0020 +#define PEX_PF0_PME_MES_DR_LUD (1 << 7) +#define PEX_PF0_PME_MES_DR_LDD (1 << 9) +#define PEX_PF0_PME_MES_DR_HRD (1 << 10) + +#define PEX_PF0_PME_MES_IER 0xC0028 +#define PEX_PF0_PME_MES_IER_LUDIE (1 << 7) +#define PEX_PF0_PME_MES_IER_LDDIE (1 << 9) +#define PEX_PF0_PME_MES_IER_HRDIE (1 << 10) + #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev) struct ls_pcie_ep_drvdata { @@ -30,8 +46,90 @@ struct ls_pcie_ep { struct dw_pcie *pci; struct pci_epc_features *ls_epc; const struct ls_pcie_ep_drvdata *drvdata; + u8 max_speed; + u8 max_width; + bool big_endian; + int irq; }; +static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) +{ + struct dw_pcie *pci = pcie->pci; + + if (pcie->big_endian) + return ioread32be(pci->dbi_base + offset); + else + return ioread32(pci->dbi_base + offset); +} + +static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, + u32 value) +{ + struct dw_pcie *pci = pcie->pci; + + if (pcie->big_endian) + iowrite32be(value, pci->dbi_base + offset); + else + iowrite32(value, pci->dbi_base + offset); +} + +static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) +{ + struct ls_pcie_ep *pcie = (struct ls_pcie_ep *)dev_id; + struct dw_pcie *pci = pcie->pci; + u32 val; + + val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); + if (!val) + return IRQ_NONE; + + if (val & PEX_PF0_PME_MES_DR_LUD) + dev_info(pci->dev, "Detect the link up state !\n"); + else if (val & PEX_PF0_PME_MES_DR_LDD) + dev_info(pci->dev, "Detect the link down state !\n"); + else if (val & PEX_PF0_PME_MES_DR_HRD) + dev_info(pci->dev, "Detect the hot reset state !\n"); + + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writew_dbi(pci, PCIE_LINK_CAP, + (pcie->max_width << MAX_LINK_W_SHIFT) | + pcie->max_speed); + dw_pcie_dbi_ro_wr_dis(pci); + + ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); + + return IRQ_HANDLED; +} + +static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep *pcie, + struct platform_device *pdev) +{ + u32 val; + int ret; + + pcie->irq = platform_get_irq_byname(pdev, "pme"); + if (pcie->irq < 0) { + dev_err(&pdev->dev, "Can't get 'pme' irq.\n"); + return pcie->irq; + } + + ret = devm_request_irq(&pdev->dev, pcie->irq, + ls_pcie_ep_event_handler, IRQF_SHARED, + pdev->name, pcie); + if (ret) { + dev_err(&pdev->dev, "Can't register PCIe IRQ.\n"); + return ret; + } + + /* Enable interrupts */ + val = ls_lut_readl(pcie, PEX_PF0_PME_MES_IER); + val |= PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE | + PEX_PF0_PME_MES_IER_LUDIE; + ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val); + + return 0; +} + static const struct pci_epc_features* ls_pcie_ep_get_features(struct dw_pcie_ep *ep) { @@ -125,6 +223,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) struct ls_pcie_ep *pcie; struct pci_epc_features *ls_epc; struct resource *dbi_base; + int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -155,9 +254,20 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) pci->ep.ops = &ls_pcie_ep_ops; + pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); + + pcie->max_speed = dw_pcie_readw_dbi(pci, PCIE_LINK_CAP) & + MAX_LINK_SP_MASK; + pcie->max_width = (dw_pcie_readw_dbi(pci, PCIE_LINK_CAP) >> + MAX_LINK_W_SHIFT) & MAX_LINK_W_MASK; + platform_set_drvdata(pdev, pcie); - return dw_pcie_ep_init(&pci->ep); + ret = dw_pcie_ep_init(&pci->ep); + if (ret) + return ret; + + return ls_pcie_ep_interrupt_init(pcie, pdev); } static struct platform_driver ls_pcie_ep_driver = {