From patchwork Tue Jan 24 12:47:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 13114012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE019C25B4E for ; Tue, 24 Jan 2023 12:47:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234066AbjAXMrz (ORCPT ); Tue, 24 Jan 2023 07:47:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234030AbjAXMre (ORCPT ); Tue, 24 Jan 2023 07:47:34 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D49D41B43 for ; Tue, 24 Jan 2023 04:47:31 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id z5so13761000wrt.6 for ; Tue, 24 Jan 2023 04:47:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pywIegW9eTFYpCgiSEhnm89XSaX/bFKZs84OM3tl29Y=; b=cA26c5kCtvhC0Znzr1jTuWvhIegH3OHEhXeMAyOhqNDfEqYEq94gEi7IBXQA4GhlSW Ek+VL5v4nZzuwd2EBjP5lmfTnDxyZW4V9Q3/QGLuFS6QGjsnF00GNxXX+Q4a9Oukpy5o P7piFzwjEMEJFJMa+hQuJbIPJF/7iUmPWC2HCVJq8OdZHAmA04HoGB0KdcV1aQTv6yAd klLsAaFdTgLR1dB6FxKoR4AFRgiOfE1uWjYk2C/Q/Qzn334BfvA49hQMumLnN9/qM7a0 t7T3VeWlaZYt90sstA9JqPrU2mqKmTl4m7eEDc5Yp4QQNMDS78ZT+HfU1ZeAA5Bn3+d9 aECQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pywIegW9eTFYpCgiSEhnm89XSaX/bFKZs84OM3tl29Y=; b=ipbrc8/URyiRd83fMJpzzIEUpDoERA0LtseR1A1pC51XedBI3+FW7YwM/1zUUR2qjO nGxu+z/G2YA5xfJi/+CJfcSup16qcmJWllxZ1kNYNiWjxAwraA1GthxKlrRpwqBnTrWY x4UMmANubGgcvpXjDAGrA0H/mUirQQVrJfHuwPruDtArb4Qr0HDrt2WQQZq1C0groUF6 4Zrr4A4maqhcCSV0sAywdpQ6z53gLreXKaLvTeQsP91+GoTMm/ELvY9qAAmVlc1tcD0A n3VIanF5NbHKyQdz8hQeVriwReD3K4wkjNmmGe5RunvuwVDyo8LkQmybsB0v+rlu43Bj V0Ww== X-Gm-Message-State: AFqh2krTMKEXZ6raOMXLzwBVBnX8YCtIXtw+VBduc0dd0EUikszmVTb6 fDVWzlwuQLQ+hKWxXkSjRCmaBA== X-Google-Smtp-Source: AMrXdXu1k2AeaXgCDlq0xypOEeQHHAaLPn5IoYo7JjLhubm7KwCiDWQryQprYUqVKjFeOEgNM+rBEg== X-Received: by 2002:adf:e9d2:0:b0:2bd:e6f5:5122 with SMTP id l18-20020adfe9d2000000b002bde6f55122mr23738937wrn.65.1674564450548; Tue, 24 Jan 2023 04:47:30 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id a5-20020a5d5705000000b002bdbde1d3absm1766840wrv.78.2023.01.24.04.47.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 04:47:30 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-phy@lists.infradead.org, Dmitry Baryshkov Subject: [PATCH v5 06/12] phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets Date: Tue, 24 Jan 2023 14:47:08 +0200 Message-Id: <20230124124714.3087948-7-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124124714.3087948-1-abel.vesa@linaro.org> References: <20230124124714.3087948-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new qserdes TX RX PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- This patchset relies on the following patchset: https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ The v4 of this patch is: https://lore.kernel.org/all/20230119140453.3942340-7-abel.vesa@linaro.org/ Changes since v4: * none Changes since v3: * added Dmitry's R-b tag Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested .../phy-qcom-qmp-qserdes-txrx-v6_20.h | 45 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 1 + 2 files changed, 46 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h new file mode 100644 index 000000000000..5385a8b60970 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_ + +#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 +#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac +#define QSERDES_V6_20_TX_LANE_MODE_1 0x78 +#define QSERDES_V6_20_TX_LANE_MODE_2 0x7c +#define QSERDES_V6_20_TX_LANE_MODE_3 0x80 + +#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08 +#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c +#define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20 +#define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34 +#define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c +#define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0 +#define QSERDES_V6_20_RX_DFE_3 0xb4 +#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8 +#define QSERDES_V6_20_RX_GM_CAL 0x10c +#define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120 +#define QSERDES_V6_20_RX_SIGDET_ENABLES 0x148 +#define QSERDES_V6_20_RX_PHPRE_CTRL 0x188 +#define QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x194 +#define QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc +#define QSERDES_V6_20_RX_MODE_RATE2_B0 0x1f4 +#define QSERDES_V6_20_RX_MODE_RATE2_B1 0x1f8 +#define QSERDES_V6_20_RX_MODE_RATE2_B2 0x1fc +#define QSERDES_V6_20_RX_MODE_RATE2_B3 0x200 +#define QSERDES_V6_20_RX_MODE_RATE2_B4 0x204 +#define QSERDES_V6_20_RX_MODE_RATE2_B5 0x208 +#define QSERDES_V6_20_RX_MODE_RATE2_B6 0x20c +#define QSERDES_V6_20_RX_MODE_RATE3_B0 0x210 +#define QSERDES_V6_20_RX_MODE_RATE3_B1 0x214 +#define QSERDES_V6_20_RX_MODE_RATE3_B2 0x218 +#define QSERDES_V6_20_RX_MODE_RATE3_B3 0x21c +#define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220 +#define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224 +#define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 760de4c76e5b..e5974e6caf51 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -23,6 +23,7 @@ #include "phy-qcom-qmp-qserdes-com-v6.h" #include "phy-qcom-qmp-qserdes-txrx-v6.h" +#include "phy-qcom-qmp-qserdes-txrx-v6_20.h" #include "phy-qcom-qmp-qserdes-pll.h"