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Fri, 19 May 2023 05:59:49 -0500 From: Thippeswamy Havalige To: , , , , , CC: , , , , , Thippeswamy Havalige Subject: [PATCH v3 2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Date: Fri, 19 May 2023 16:29:00 +0530 Message-ID: <20230519105901.2399452-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519105901.2399452-1-thippeswamy.havalige@amd.com> References: <20230519105901.2399452-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT070:EE_|BY5PR12MB4853:EE_ X-MS-Office365-Filtering-Correlation-Id: b7d08270-3676-4ee8-38c4-08db58582d10 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tE9yxlyZ/HMZiRTiAVec+rKKH8JT+OEtX9E9pRjLSpSy56XU/jkVeKTanVfAPEHzkfXIL029Dd//cCF9h1F8bbVOBjYJtox52QLyloYjyejRqRBtqYEfpbaWAcVo0ADstglyFH15OHOFzwexV3ytyk2u0TohJdQax4gej+94iajlgTAws5lNZKAYYjnJeh45nIx63JkU0dH4FdF4AqJZfke6cdoZkYJSgrQIQYralOrbPeUCncIDjwvY9nkwF9ATdy2xKustt3IoH1tYrG1LWjjg4aorrSC+6YTonhWP7SIO0F1wkhrDEcUaCCu6Kr92EB1o9GVsWdGAk2Dc47jWlbF0gRVqAWyiTsMxXsJpfgvMz6V2vFeS48fhd/ciW/MTaSYhtXzh7MYAcgsJM8ToAJG9OjQknHxJVICSVX1iOht8IanQqF4dr2cpzk9kFIqqHPx5s4ZNgFlt0X6fX1yrTlRNlGglsK3IA106wmCC7uMwks+Hgy3oe0SZgJdlPh5bVbyW3ze+/0yAAamw5PZDIK9BW6Yd0+nL5AWFozzBAiUKdZYvfD10GI2ZNkjDRChvfunii4lPyRa4NRJ4l1dYa+tlwLGZHdzRdl9Ys5e5UDgUNSHWHrwSakzj24RS9rPqgGE8Rng9dsyyA/vfFYinC4G5dnDg845YXMEbkUHmE3AMs9Fc3rnLBz1i1moNku7AgwDdSs/jMsYw99PQimeAyYxfi1TwqvnkqXqFe7xdxocdtP1u/fkliBvIJY3R+g2YtCvqUAvimwWmero5eGDfifmbkpyuHhlvHMbZSw9uAx0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(396003)(136003)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(40460700003)(6666004)(41300700001)(44832011)(26005)(1076003)(36860700001)(5660300002)(2616005)(36756003)(47076005)(82310400005)(186003)(336012)(426003)(2906002)(86362001)(966005)(356005)(81166007)(8676002)(8936002)(40480700001)(82740400003)(478600001)(70586007)(70206006)(4326008)(54906003)(110136005)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2023 10:59:53.7742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7d08270-3676-4ee8-38c4-08db58582d10 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT070.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4853 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add YAML dtschemas of Xilinx XDMA Soft IP PCIe Root Port Bridge dt binding. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes for v3: - Fixed compatible string issue. - Modified ranges property description to maxItems. - Modified address-cell property of interrupt-controller child node. changes for v2: - None .../bindings/pci/xlnx,xdma-host.yaml | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml new file mode 100644 index 000000000000..ec46712c3e7b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx XDMA PL PCIe Root Port Bridge + +maintainers: + - Thippeswamy Havalige + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: xlnx,xdma-host-3.00 + + reg: + maxItems: 1 + + ranges: + maxItems: 2 + + interrupts: + items: + - description: interrupt asserted when miscellaneous interrupt is received. + - description: msi0 interrupt asserted when an MSI is received. + - description: msi1 interrupt asserted when an MSI is received. + + interrupt-names: + items: + - const: misc + - const: msi0 + - const: msi1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + properties: + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + required: + - interrupt-controller + - "#address-cells" + - "#interrupt-cells" + + additionalProperties: false + +required: + - compatible + - reg + - ranges + - interrupts + - interrupt-map + - interrupt-map-mask + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@a0000000 { + compatible = "xlnx,xdma-host-3.00"; + reg = <0x0 0xa0000000 0x0 0x10000000>; + ranges = <0x2000000 0x0 0xB0000000 0x0 0xB0000000 0x0 0x1000000>, + <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = , , + ; + interrupt-names = "misc", "msi0", "msi1"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller ; + }; + }; + };