From patchwork Mon Jun 19 15:04:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13284687 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05161C001B3 for ; Mon, 19 Jun 2023 15:06:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229767AbjFSPGO (ORCPT ); Mon, 19 Jun 2023 11:06:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231417AbjFSPFU (ORCPT ); Mon, 19 Jun 2023 11:05:20 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F15F810E2 for ; Mon, 19 Jun 2023 08:04:44 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-25df7944f60so2775733a91.2 for ; Mon, 19 Jun 2023 08:04:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687187084; x=1689779084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y/GAaoCJDXRESh8SzkgobGj/lkVGqp4sgMGqg7raF+w=; b=V9wXOuC0u6MhserqB+G6difAW8y4vzCRO18OAHl8pZnY48vHjoerHjTRsy+IVJqNcJ yRJh/pMYCSaxpRbcXAZFUsGHkqN5noXwbP/l5hlnO5r2kADG2CM0AQW5UtMji3Ppz+HK oTskUMwOIwrFfONX8n3SF9RSKCh3AOC19NJ12xPMVmOneKEpTzxmfyUAx+2pfBn5+AlB g1u2B4xEfnBiJo3IUVVaYLZuLmzh/0on5msGUMn1RuePtdM8wq4HTxrWZJupUxO/9MAd VhoNpR/Nu+8I11s4QzL5bA60jEWGz6kuipBuN5+njDVf+6Q8C3i7xutqeRTpI6rTbNPW wmAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687187084; x=1689779084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y/GAaoCJDXRESh8SzkgobGj/lkVGqp4sgMGqg7raF+w=; b=IW4e5i/kIZrZMcS/eV6+X/ts54LBuCbDQk1N0G3wJxwQpRXfs/oQhKsdQiIUnO8//C QPqQATDF5z1jcPoA92/2BteFQOyDvajufS+1GZSMYHWj5dofKFX4fG8LqPxUBw73o/TI 5ZXbRbyND8p08hRUm33PGdanMubipgHhBzgtTlPNcSzVDYkzIlp/PxeuAn8F1WXkQCmj 5xjPTkBJQTlpTPNnXxd1T+YPVbvPNr9OVm2pcOh/V/PIzxrnbnZLWCQPuo3RF/o7s5ur 9icdLIvTER4wIh8iEfKC0q2NbbW9IYdRpgM7ryeengroylhO0ND5D/B2XK7BLSAVzqcV Rn3w== X-Gm-Message-State: AC+VfDxDSXtulLPJopW8jZwKRlsWgG2PXAfwOAlm7tO/ei8levvgrias x+dBmWemEETWLa+GHBBk8Lrf X-Google-Smtp-Source: ACHHUZ6Lgv+CRaeHvpmMJL0dObGrC9m7WE8tCgI+82+fGfhWauNyHfgIcYA5lk5e88NN9cFcN1NqLA== X-Received: by 2002:a17:90a:44:b0:260:a45e:751a with SMTP id 4-20020a17090a004400b00260a45e751amr1973170pjb.25.1687187084355; Mon, 19 Jun 2023 08:04:44 -0700 (PDT) Received: from localhost.localdomain ([117.217.183.37]) by smtp.gmail.com with ESMTPSA id 10-20020a17090a19ca00b0025efaf7a0d3sm2765480pjj.14.2023.06.19.08.04.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 08:04:44 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v4 7/9] PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0 Date: Mon, 19 Jun 2023 20:34:06 +0530 Message-Id: <20230619150408.8468-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> References: <20230619150408.8468-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The post init sequence of IP v2.4.0 is same as v2.3.2. So let's reuse the v2.3.2 sequence which now also disables hotplug capability of the controller as it is not at all supported on any SoCs making use of this IP. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 30 +------------------------- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 9c8dfd224e6e..e6db9e551752 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -703,34 +703,6 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) return 0; } -static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) -{ - u32 val; - - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PARF_PHY_CTRL); - val &= ~PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); - - /* change DBI base address */ - writel(0, pcie->parf + PARF_DBI_BASE_ADDR); - - /* MAC PHY_POWERDOWN MUX DISABLE */ - val = readl(pcie->parf + PARF_SYS_CTRL); - val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; - writel(val, pcie->parf + PARF_SYS_CTRL); - - val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |= BYPASS; - writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - - val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - val |= EN; - writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - - return 0; -} - static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; @@ -1276,7 +1248,7 @@ static const struct qcom_pcie_ops ops_2_3_2 = { static const struct qcom_pcie_ops ops_2_4_0 = { .get_resources = qcom_pcie_get_resources_2_4_0, .init = qcom_pcie_init_2_4_0, - .post_init = qcom_pcie_post_init_2_4_0, + .post_init = qcom_pcie_post_init_2_3_2, .deinit = qcom_pcie_deinit_2_4_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, };