From patchwork Fri Jun 23 14:40:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13290747 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD892EB64DD for ; Fri, 23 Jun 2023 14:41:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231938AbjFWOlU (ORCPT ); Fri, 23 Jun 2023 10:41:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231665AbjFWOlT (ORCPT ); Fri, 23 Jun 2023 10:41:19 -0400 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFD982688 for ; Fri, 23 Jun 2023 07:41:09 -0700 (PDT) Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-7624e8ceef7so60290285a.2 for ; Fri, 23 Jun 2023 07:41:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1687531268; x=1690123268; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=H/MnZlXk/4MfIX0Zs4hYPeMhGkoL8SprRM9WTvKMY24=; b=BttqBtgeyKQYKgfwjS8Ne9zM/0TI10iQGX8kNemb/icXbKrzzWhR01zccE21L8dlOe WFCVCCbByiInJQo9n0kcr59w89i5M9TTwMR6CIN9oCyHnTBVEsQeY+SSIH6OeAy9youA 4rdYL6XkNIghJTPMYIyWYZBIPUUn55a8SFKV8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687531268; x=1690123268; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=H/MnZlXk/4MfIX0Zs4hYPeMhGkoL8SprRM9WTvKMY24=; b=VI2yAIHadbC15O8bMfxwtbwhcuiKYEVuNJ2liD156PWTz/m6TPjKs0xzgGoVCDjAEe ebMdu1RmrC3TpMa8pRtVGgL1Wys6sLvgbm/8HRFhv/YTR380nWhRzDf4UT4jrRaKwHjr mWS5Uqtxpg2MO71lgsMVH79zQPj/qW/MnRafk1ewM+6fW6S3hYWh9l+69RkLCnhGC+AU Ye77Vj6AkXKYE92p77c1dtTaw00Vjokmau+I/W3p1P1BA1ZVem1HGr2gBbhxeBFcGRIU RH0a08/atzxOfvxrEoFtb3C//x8VYECOH3rT/q1EXxmuDxL8MjIdJ8zYL98WHgNGL9Xo b8wQ== X-Gm-Message-State: AC+VfDyV0L88ZB9NlEMHMXldFcrZ1H1nCWJPxI/qxIClea3H6mZ0lCTE 86q+0HCNk5VnmqgrvT0ZO7GmXC0gxhln7RApSsuodocIfoFCOs6QQ3WZIXOwY2Uy0Jsr1t3c8Ty GNdCDLu5+63NyWv9XOQTOlSaF5Lt7oW8x/FCFzjO1PQq7dIyqD60gZ81h0OWxFtYFEESBPjYPbn op4v6cqZ/A4Q== X-Google-Smtp-Source: ACHHUZ6VEUGWHyC6gT/qBlxdtFs8HESOkMiVWwwv0lzZBtEqaLYNovEbLqSls92mOSWoka1L+bDJrg== X-Received: by 2002:a05:620a:424d:b0:75b:23a1:3606 with SMTP id w13-20020a05620a424d00b0075b23a13606mr15726420qko.23.1687531268377; Fri, 23 Jun 2023 07:41:08 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id i18-20020a05620a145200b007625382f4ccsm4564613qkl.69.2023.06.23.07.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 07:41:07 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Jim Quinlan , Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property Date: Fri, 23 Jun 2023 10:40:54 -0400 Message-Id: <20230623144100.34196-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230623144100.34196-1-james.quinlan@broadcom.com> References: <20230623144100.34196-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This commit adds the boolean "brcm,enable-l1ss" property: The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- requires the driver probe() to deliberately place the HW one of three CLKREQ# modes: (a) CLKREQ# driven by the RC unconditionally (b) CLKREQ# driven by the EP for ASPM L0s, L1 (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS). The HW+driver can tell the difference between downstream devices that need (a) and (b), but does not know when to configure (c). All devices should work fine when the driver chooses (a) or (b), but (c) may be desired to realize the extra power savings that L1SS offers. So we introduce the boolean "brcm,enable-l1ss" property to inform the driver that (c) is desired. Setting this property only makes sense when the downstream device is L1SS-capable and the OS is configured to activate this mode (e.g. policy==powersupersave). This property is already present in the Raspian version of Linux, but the upstream driver implementation that follows adds more details and discerns between (a) and (b). Signed-off-by: Jim Quinlan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7e15aae7d69e..8b61c2179608 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -64,6 +64,15 @@ properties: aspm-no-l0s: true + brcm,enable-l1ss: + description: Indicates that PCIe L1SS power savings + are desired, the downstream device is L1SS-capable, and the + OS has been configured to enable this mode. For boards + using a mini-card connector, this mode may not meet the + TCRLon maximum time of 400ns, as specified in 3.2.5.2.2 + of the PCI Express Mini CEM 2.0 specification. + type: boolean + brcm,scb-sizes: description: u64 giving the 64bit PCIe memory viewport size of a memory controller. There may be up to