From patchwork Thu Jul 20 13:58:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13320559 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8671BC0015E for ; Thu, 20 Jul 2023 13:59:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231781AbjGTN7B (ORCPT ); Thu, 20 Jul 2023 09:59:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231759AbjGTN7A (ORCPT ); Thu, 20 Jul 2023 09:59:00 -0400 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2064.outbound.protection.outlook.com [40.107.22.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50E511BFC; Thu, 20 Jul 2023 06:58:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EuOvbtORuQbONwj/CQ5pdmFzwRJXIj/qYOcMuh4hckRGwf/gw9GDMaoydHyYdDN4qOr8ZdfiiAGWn4uAzF/QSpEe+nejPqFxctISStwunaAEa5BHvTouHB3Q+fVgOsAJP8uy8V+uy80DI9voxexeO1boGKaJ2AiN+BdKqFP5BGPXPUoWyA6/MatJOVCrwNFGLEsoSlbUvj1nNMVEmNIckXR99y0C5h8me8whmD62l+DtD6OaG7DY2WeJmUFxq/gApN+dlcefc2R/+Dm5eOyuW/1L72oa2HJOyKXlZ9xVOBsvxJBNfNEMBKjjSHB3IsrKtzj46/fs50vK1gy1IujqmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Vvvbx1BEBpinxsumUX48rt0sTeC+wt2vpJoWkExyF8s=; b=FsKIwVXt9R2loVF0ctRx7OeNm7fIsFBQUCVQVwwSTdlg/bTdIEwn7PFg6O/KKgdhyS8juLqx5TiezwFLskZjhGsXTbhUUek2ntTfyAbcMGkOjryM9t/CbBtsVYU8118MOPztH4Ntqf2+2SoGKtL2GW062X7C4OH/mp8YGM6eCQ5NhpKLjib8UsEBORkJrks1KeIXLmM/oygnstRfNIxdtQ/kZEZwhKEagakuLGjSBhtwH2pbcuwFG60Oh5rpiOTYpOrVuKf9IP0VxvkOPgpnOPzjLieKs1zrlOPCytGjGXdAI9RXuCc9j5W2sE5HQrzawxjw432T5vPsW81wtyFhAw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Vvvbx1BEBpinxsumUX48rt0sTeC+wt2vpJoWkExyF8s=; b=VyWIFSNUchTMXIR6jVBq9j/HPP2hROpEIufTxMzzbuazefrTEMHbmDh23uSoyskqRA9yeJT6IuRnezhgf7uuUVCzad4ZeKlcisjaGWRlvQ5u1PtD7tEKXddS5vCMYwoZXSDENTrd3O1Kp7zQ7BU4cjlGkIuvWGhgf6P/MoKPSlc= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by GVXPR04MB9973.eurprd04.prod.outlook.com (2603:10a6:150:112::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.31; Thu, 20 Jul 2023 13:58:58 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::d0d5:3604:98da:20b1]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::d0d5:3604:98da:20b1%7]) with mapi id 15.20.6609.024; Thu, 20 Jul 2023 13:58:58 +0000 From: Frank Li To: frank.li@nxp.com, lpieralisi@kernel.org Cc: Zhiqiang.Hou@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kernel-janitors@vger.kernel.org, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, mani@kernel.org, markus.elfring@web.de, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com, xiaowei.bao@nxp.com Subject: [PATCH v4 2/2] PCI: layerscape: Add the workaround for lost link capabilities during reset. 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Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support") Acked-by: Manivannan Sadhasivam Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Signed-off-by: Frank Li --- change from v3 to v4 - fix wrong commit a debug code, change pr_err to pr_dbg change from v2 to v3 - fix subject typo capabilities change from v1 to v2: - add comments at restore register - add fixes tag - dw_pcie_writew_dbi to dw_pcie_writel_dbi .../pci/controller/dwc/pci-layerscape-ep.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index e0969ff2ddf7..b1faf41a2fae 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -45,6 +45,7 @@ struct ls_pcie_ep { struct pci_epc_features *ls_epc; const struct ls_pcie_ep_drvdata *drvdata; int irq; + u32 lnkcap; bool big_endian; }; @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) struct ls_pcie_ep *pcie = dev_id; struct dw_pcie *pci = pcie->pci; u32 val, cfg; + u8 offset; val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); @@ -81,6 +83,19 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) return IRQ_NONE; if (val & PEX_PF0_PME_MES_DR_LUD) { + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + /* + * The values of the Maximum Link Width and Supported Link + * Speed from the Link Capabilities Register will be lost + * during link down or hot reset. Restore initial value + * that configured by the Reset Configuration Word (RCW). + */ + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); + dw_pcie_dbi_ro_wr_dis(pci); + cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); cfg |= PEX_PF0_CFG_READY; ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); @@ -216,6 +231,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) struct ls_pcie_ep *pcie; struct pci_epc_features *ls_epc; struct resource *dbi_base; + u8 offset; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); @@ -252,6 +268,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + ret = dw_pcie_ep_init(&pci->ep); if (ret) return ret;