From patchwork Mon Sep 18 10:22:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13389371 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 160F9CD37B0 for ; Mon, 18 Sep 2023 10:24:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234383AbjIRKYU (ORCPT ); Mon, 18 Sep 2023 06:24:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241124AbjIRKX4 (ORCPT ); Mon, 18 Sep 2023 06:23:56 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1673ED9 for ; Mon, 18 Sep 2023 03:23:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1695032630; x=1726568630; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=cS4ybwbqfyLBdznvtOWvMo0l9S0n2GVGkyFIttLSb3k=; b=hOMqTRUlKCGHYwNkrgg7lVtmECgOEfpcLNj2/qIDnlwxTS0pYT8zyrrv UlzMXdsKt8upge70MAvaTlPBTSaMozVaUwCwNj4jqAiBTlI9RhkZRlhfo 44IPg4H5XG9Ibkc4UhOYROXRYxTnD8o2GsZEqqtQrkglRi4bozpCw62OZ cBpOCD+gZRYv0MekzOFFykWu8udcFDLb3VXcXC4fMmG2zyBMCFPkJXED7 boOvHHt/+xnE2YzF+RZbfmJZ7rQU5B1BOaCHcFuUfxgUgxAilPy4rcmrK sJUE+ZFKCfCfs7iLy9abHM9xJRt0Eseqz6D2ACHV67RZW4RYRG5S/hmbX w==; X-CSE-ConnectionGUID: 7Em7OOITQwKiKSoED66vMw== X-CSE-MsgGUID: hyKhDgBAQaOmVXYMUyCiIw== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.02,156,1688454000"; d="scan'208";a="5204121" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 Sep 2023 03:23:49 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 18 Sep 2023 03:23:22 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 18 Sep 2023 03:23:20 -0700 From: Conor Dooley To: CC: , , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Subject: [PATCH v1] PCI: dwc: convert SOC_SIFIVE to ARCH_SIFIVE Date: Mon, 18 Sep 2023 11:22:47 +0100 Message-ID: <20230918-safeness-cornflake-62278bc3aaaa@wendy> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1058; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=cS4ybwbqfyLBdznvtOWvMo0l9S0n2GVGkyFIttLSb3k=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKkcKp9/lFxdLZ5atvB8a3TA5NIfxtveL9Fca2507sX7p2cr uMr5O0pZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCRc6GMDFv/67s+YNVZKK/88bLy0X sh1/7Lnz89y2CitujhpNIFvzwZGVZLBkxMS3JcbLqYvbpQ+pVttk/9/cyiZuX6iLqFO/I9mQE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the use of such symbols on other architectures, convert the SiFive PCI drivers to use the newer symbol. Signed-off-by: Conor Dooley --- CC: Lorenzo Pieralisi CC: Krzysztof Wilczyński CC: Rob Herring CC: Bjorn Helgaas CC: linux-pci@vger.kernel.org --- drivers/pci/controller/dwc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index ab96da43e0c2..58234334bcc2 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -311,7 +311,7 @@ config PCI_EXYNOS config PCIE_FU740 bool "SiFive FU740 PCIe controller" depends on PCI_MSI - depends on SOC_SIFIVE || COMPILE_TEST + depends on ARCH_SIFIVE || COMPILE_TEST select PCIE_DW_HOST help Say Y here if you want PCIe controller support for the SiFive