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Thu, 5 Oct 2023 09:42:06 -0700 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 5 Oct 2023 11:42:03 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , , , , Thippeswamy Havalige Subject: [PATCH v5 RESEND 4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Date: Thu, 5 Oct 2023 22:10:51 +0530 Message-ID: <20231005164051.984254-5-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005164051.984254-1-thippeswamy.havalige@amd.com> References: <20231005164051.984254-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D5:EE_|IA1PR12MB7566:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c90cb71-aaed-4b09-56b7-08dbc5c203cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9or5TypMO1/wkJGnRZopMkM4ubMavyraMdKunyT4VCs0jMZa1+r19CUhq77IkTBg4xcFKLT8bCLOnPSLbCj6IJPMcdnR7XylOLAfx2f/pPHOVm7RFNJxBVLfG5CGJi/5t5kYYU1NiHDOisXAbQ/X2ioqfcx832u5SgV6ELJi0lmCU0iiKdqi1BAfv8waXyTZnL0FpcuW1thKu2noxQzxHLURern9qTzuPl7dS4N+q/JVKVYw6xf5m2fgTWrbKPPEHp99XT1DP5yR73kmSaM2n6qbvyns6D4+Gh2VjBAlGarmPkU0SLCn5pGTEkPCGLbbFW9Xma43SmSIz1JprPfX9OTSPrjj8EXV+teYjD4H3ub6nczLMk/4p2PoTkUkHi48XWj2D8G4GDY7FHJdxtxA3U6rj5wYluVogjLFpRFWQTFicTj+1wIxo7ODBPrxS79cf/shi1+Qh/CHwPsMzkRtuUFQcigJhC7PPBBodkdpBueTDgXnMXFviMnqac9N5+xVitEfwoTMuN03y1fJC9FyoEzlqEqqG6gWIIHpRIvpBQUfQ1FJCCRtzw1pF3y1OX9LrENZL6JZ5pcKE7S7Q8puX8P47jk75wbt3+JI3SMfsexc0aX209ik6ApNOOB7ca/afWwhiMBejGchocGDOICMIxdBiLAje/ooHTHaijpkaHP/aBS7VYGlMo25vIQa1KV3EPJkGWNY5GlXN0SgcFGeSPoFV5dVAzOhv3knz6YnEOQTta86EdbfbvUBFqNsgmCXdNeB644MloLnBppfe6rqHfb+XY3dTuLIJuNIEmwXJL0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(39860400002)(346002)(396003)(230922051799003)(1800799009)(186009)(451199024)(82310400011)(64100799003)(40470700004)(46966006)(36840700001)(40480700001)(40460700003)(2906002)(316002)(26005)(54906003)(426003)(83380400001)(44832011)(7416002)(1076003)(478600001)(336012)(2616005)(5660300002)(4326008)(70206006)(8676002)(6666004)(110136005)(47076005)(70586007)(8936002)(356005)(36860700001)(86362001)(4744005)(81166007)(41300700001)(36756003)(82740400003)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2023 16:42:07.9429 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c90cb71-aaed-4b09-56b7-08dbc5c203cf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7566 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige --- changes in v5: None. --- drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0..e307aceba5c9 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)