From patchwork Wed Oct 18 11:32:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13426896 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70E21CDB47E for ; Wed, 18 Oct 2023 11:33:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229884AbjJRLdr (ORCPT ); Wed, 18 Oct 2023 07:33:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229977AbjJRLdp (ORCPT ); Wed, 18 Oct 2023 07:33:45 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6D35115; Wed, 18 Oct 2023 04:33:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697628823; x=1729164823; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+IUgN6qDc3zy/7h4GNa/9YgQiOVwyIUTeR+n02SRwIM=; b=lSWAU71aIUaHqUWrMunRcy8XDUWNZfk9zGNWodVyf5ut3K/O4u+Zm9Zr fPQ3yfYnvExezMnkOeHDWAjb9BrWuPkOVclLh1oulpu4Xy1yNNJsDNisw cavOtF4jVJeI6AU5mosxapsU7uaLwjcRYjvOtjZt1VqqirxZNpTC2CbTw VmHgYDmtd8BGTo0vj8SxBlqoEbPSPyrKnFbgxpel9Xj7kDsgW6jLAq9Ya r2I9LDAYs4D0oLthtKRZzCgAZr+gLzqZKPh4ikta8hpNR+hWa9Wc1tAY+ ftPGWRsKQnKdCVXvS2hIMGV526o/7BKHa9XBvq/f6mXg3Xs+37QdrKEIK A==; X-IronPort-AV: E=McAfee;i="6600,9927,10866"; a="371056710" X-IronPort-AV: E=Sophos;i="6.03,234,1694761200"; d="scan'208";a="371056710" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2023 04:33:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10866"; a="930150801" X-IronPort-AV: E=Sophos;i="6.03,234,1694761200"; d="scan'208";a="930150801" Received: from suguccin-mobl1.amr.corp.intel.com (HELO localhost) ([10.252.44.63]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2023 04:33:39 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Jonathan Cameron , Tom Joseph , Lorenzo Pieralisi , linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 1/7] PCI: cadence: Use FIELD_GET() Date: Wed, 18 Oct 2023 14:32:48 +0300 Message-Id: <20231018113254.17616-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20231018113254.17616-1-ilpo.jarvinen@linux.intel.com> References: <20231018113254.17616-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert open-coded variants of PCI field access into FIELD_GET() to make the code easier to understand. Signed-off-by: Ilpo Järvinen --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index b8b655d4047e..3142feb8ac19 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -3,6 +3,7 @@ // Cadence PCIe endpoint controller driver. // Author: Cyrille Pitchen +#include #include #include #include @@ -262,7 +263,7 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) * Get the Multiple Message Enable bitfield from the Message Control * register. */ - mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; + mme = FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); return mme; } @@ -394,7 +395,7 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, return -EINVAL; /* Get the number of enabled MSIs */ - mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; + mme = FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); msi_count = 1 << mme; if (!interrupt_num || interrupt_num > msi_count) return -EINVAL; @@ -449,7 +450,7 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, return -EINVAL; /* Get the number of enabled MSIs */ - mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; + mme = FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); msi_count = 1 << mme; if (!interrupt_num || interrupt_num > msi_count) return -EINVAL; @@ -506,7 +507,7 @@ static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, reg = cap + PCI_MSIX_TABLE; tbl_offset = cdns_pcie_ep_fn_readl(pcie, fn, reg); - bir = tbl_offset & PCI_MSIX_TABLE_BIR; + bir = FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset); tbl_offset &= PCI_MSIX_TABLE_OFFSET; msix_tbl = epf->epf_bar[bir]->addr + tbl_offset;