From patchwork Fri Oct 27 08:38:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13438237 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 959ACC27C46 for ; Fri, 27 Oct 2023 08:38:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235117AbjJ0Iia (ORCPT ); Fri, 27 Oct 2023 04:38:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235107AbjJ0IiX (ORCPT ); Fri, 27 Oct 2023 04:38:23 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC3F3106; Fri, 27 Oct 2023 01:38:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698395901; x=1729931901; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=SBl7gvq5bTKZ2qBWsxuRcqwqbwBEKeoZL83t6kWoQH4=; b=SFzFPe7mCYj6XvD3S4cNgadIpsou6aR/MziGFT3HHEF8QeUNr1L+xast GJgKzbrNQKZICUtEzJZNu1vFskr8/sN92HOgFDA8qX9UZQVoNIn1EPGsM RqX1cEHT2e+lou2pLm7XazRsg5aMT5EkckdC7mSWbN/dV2oWKzCzhbVvH SGktee8bnaijwEBeb1H9nc/94zl42YJGUTp0Uxlz7lmbsO4K8DDwnm0uN 8ylsuBlZbhLk0LNFWc7TQ9cWIDa/Zn6gTCCkyZ+hP4mgu7PTLk/FxUDnl YRj6Yp/z6aUo02Cjv0EXaj5XCYKqm/vAk31WPbcP3cV/WXkNXkjzvxBZ9 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10875"; a="391609777" X-IronPort-AV: E=Sophos;i="6.03,255,1694761200"; d="scan'208";a="391609777" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2023 01:38:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10875"; a="753056267" X-IronPort-AV: E=Sophos;i="6.03,255,1694761200"; d="scan'208";a="753056267" Received: from amyachev-mobl3.ccr.corp.intel.com (HELO localhost) ([10.252.49.46]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2023 01:38:18 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 1/1] PCI: Use FIELD_PREP() and remove *_SHIFT defines Date: Fri, 27 Oct 2023 11:38:11 +0300 Message-Id: <20231027083811.9200-1-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Instead of open-coded masking and shifting with PCI_CONF1_* bitfields, use GENMASK() and FIELD_PREP(), and then remove the *_SHIFT defines that are no longer needed. Signed-off-by: Ilpo Järvinen --- drivers/pci/pci.h | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 39a8932dc340..31da9fde8aca 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -2,6 +2,8 @@ #ifndef DRIVERS_PCI_H #define DRIVERS_PCI_H +#include +#include #include /* Number of possible devfns: 0.0 to 1f.7 inclusive */ @@ -797,19 +799,15 @@ static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) * Section 3.2.2.3.2, Figure 3-2, p. 50. */ -#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ -#define PCI_CONF1_DEV_SHIFT 11 /* Device number */ -#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ - -#define PCI_CONF1_BUS_MASK 0xff -#define PCI_CONF1_DEV_MASK 0x1f -#define PCI_CONF1_FUNC_MASK 0x7 +#define PCI_CONF1_BUS_MASK GENMASK(23, 16) +#define PCI_CONF1_DEV_MASK GENMASK(15, 11) +#define PCI_CONF1_FUNC_MASK GENMASK(10, 8) #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ #define PCI_CONF1_ENABLE BIT(31) -#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) -#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) -#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) +#define PCI_CONF1_BUS(x) FIELD_PREP(PCI_CONF1_BUS_MASK, (x)) +#define PCI_CONF1_DEV(x) FIELD_PREP(PCI_CONF1_DEV_MASK, (x)) +#define PCI_CONF1_FUNC(x) FIELD_PREP(PCI_CONF1_FUNC_MASK, (x)) #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ @@ -827,9 +825,8 @@ static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) * are used for specifying additional 4 high bits of PCI Express register. */ -#define PCI_CONF1_EXT_REG_SHIFT 16 -#define PCI_CONF1_EXT_REG_MASK 0xf00 -#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) +#define PCI_CONF1_EXT_REG_MASK GENMASK(27, 24) +#define PCI_CONF1_EXT_REG(x) FIELD_PREP(PCI_CONF1_EXT_REG_MASK, (x) >> 8) #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \