From patchwork Wed Nov 22 06:04:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13464087 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A605415AE3 for ; Wed, 22 Nov 2023 06:04:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GwBaS0CK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8E72C433CD; Wed, 22 Nov 2023 06:04:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1700633068; bh=vLKniB7pmXsD0MDHFe8N5T7V8n7++oSIsHdTVRMJkB8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GwBaS0CKeQVfNthUwlNEXL2qxPNoaG+pB7XiQdNb9qwDiGik7mmubKT7y8rgfjjda HxThCESplS3O18Fl9p+PAlBgueBhY5zgU0JrRkUPe41fIpBKGxZujHSOmsM9g6HCPw a2kvBApGolM/DigpO0obZcXJxChNQuZyGbONMqQTqAgU2AnOq+yv27MjmesCM1WuB0 8gKMrjZL1jq3zE6wAWxDLL0wvSXVd6Y3QkYCFoSoKVWVfJzIf+V8s40NWj8nTEyBRk +DjC65GiteqxwovLNatbXRpRL2KJEqf3QDczm8qFgW10eLhdMyGpLyzwsizon4Lhpi Rot8yb8dhxhZA== From: Damien Le Moal To: linux-pci@vger.kernel.org, Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Lorenzo Pieralisi , Kishon Vijay Abraham I , Manivannan Sadhasivami , Serge Semin , Yoshihiro Shimoda Subject: [PATCH v4 11/16] PCI: dw-rockchip: Rename rockchip_pcie_legacy_int_handler() Date: Wed, 22 Nov 2023 15:04:01 +0900 Message-ID: <20231122060406.14695-12-dlemoal@kernel.org> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122060406.14695-1-dlemoal@kernel.org> References: <20231122060406.14695-1-dlemoal@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rename the function rockchip_pcie_legacy_int_handler() to rockchip_pcie_intx_handler() to match the code managing INTX interrupts (e.g. intx_domain_ops) and the term used in the PCI specifications. Signed-off-by: Damien Le Moal Reviewed-by: Christoph Hellwig --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 2fe42c70097f..2b3923c52827 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -72,7 +72,7 @@ static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, writel_relaxed(val, rockchip->apb_base + reg); } -static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) +static void rockchip_pcie_intx_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); @@ -202,7 +202,7 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) if (ret < 0) dev_err(dev, "failed to init irq domain\n"); - irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, + irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler, rockchip); /* LTSSM enable control mode */