From patchwork Mon Dec 4 16:08:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13478736 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="Boy/edya" Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2077.outbound.protection.outlook.com [40.107.247.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DC0C102; Mon, 4 Dec 2023 08:08:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MxH4iqlC+Gllr+SdAZTwmzJZsSXUmWcuaE6kE7rmtq0IVxUj7HY0mjlJU5hY3eEDU9C4/oW2WHZJFJqrJ6AAI6BL89NKSYhhPEOY1YDYWkbs9xEZcazAKZxp8k/G+PXF3QOa9Al5BGJ7zcGGPGY3UqjAKHaszhqQISnPJlr0zm3JM+n56B5wM6kqf/E08kW6WYBWIXhz0Ceq6ivGsUWyXzuzrRcF9quDq703jkf53ABxfEGiXLWdZX+/fb9no4V+vckYFwJVLtUJCm26voXxdMLPSM3i6H6pishPvG8a2hcaW61H6DS9pF+9efRxOzKgp6bDJAQVKN4jGuo2kkEfGw== ARC-Message-Signature: i=1; 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b=Boy/edya7aoXKLEmU22wagGx3zTWi/aUfJBTowL2mwlwqcjuv7BRhiw5vUaHj/1p86MwRei0iRyf/HY8cOYe2m14Bgea/x85L6M2NWc6nhYullT1Z+Q2/clGr7qkfdvR+ymTDrE5H81heJ0gHoxdOI/Gf63/R/IvtaU06wcxJW0= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DBBPR04MB8057.eurprd04.prod.outlook.com (2603:10a6:10:1f1::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.22; Mon, 4 Dec 2023 16:08:56 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%6]) with mapi id 15.20.7068.022; Mon, 4 Dec 2023 16:08:56 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v6 2/4] PCI: layerscape: Add suspend/resume for ls1021a Date: Mon, 4 Dec 2023 11:08:27 -0500 Message-Id: <20231204160829.2498703-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231204160829.2498703-1-Frank.Li@nxp.com> References: <20231204160829.2498703-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR21CA0027.namprd21.prod.outlook.com (2603:10b6:a03:114::37) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DBBPR04MB8057:EE_ X-MS-Office365-Filtering-Correlation-Id: c32978ae-40cb-4e11-9511-08dbf4e35135 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mDdPMbmMSOcHYKEo7vGOnWxzTS++2BbXjrvRfBsk0qt5idOag21jauwdplWowwbKpxXqK/XliiEj+TG5jLpDvi7R/Y39wTbs+Om0SzuzunKHJwndo0aDKcAi8GtknFNi/a9xkA8yUR4kzmSYk1c7phyYU/OV0HGWUpGklwh6NzQQNnXQAvi9JvZAavM3tm1o5ZjLI5K7783a0hlo/UbCtBKyjy44zKrKdtUUvUF2nfjd+VvMgSWmzBwOj/cnOfZmAbT/mbgvrPptIRbYoqMB+CKh3L3JU3Mv2Ix+Dt/N7jerboZCt6g3F2f8zOiG7AF+nfWjb0Q/Lg2Y7Kwmlk+4fG2mEl8mZT9KzAG+AYlN8V4uh1PiF38YGlDz25s1fKwXr8Af+2tPgRI+f6Uj6EWSoeP+wfPJxxc7z7zYhtc/UWWW4HioLP2yjOBxnkNXk2hR8RcoVB44ukOoZX7lNuAqztwJBZ9wU87f8i8pNjWMZ31G3LFABwHXTSFBCcXRD2iHf/gTVAJk6lk7cnyps8Gg/D4y904497vuqvk8KBix1P7hJwEljeo9KFsqsBjPtaiTxqxvlAhZfFzCuvwbbxVO2vrT1TIIfKlGitSNh258TLBFfuRQmT5WJ7bqaNquYcJDGBT0srXA4c8+95gVQTj8Djo8VtWeJRXG1mK1XdyXYNqsJkv58pX3JMmBsVugp4lIBmBbXkB0FlC6U71w+adN90t9ie32BpXixUFWJ3nBdasHxw4ZDGsRxX0eJjy7EZy2nP0rGGsFu/HqHIpgAF61kI+RglKeggm3CgL0xxuJ+ffEbhV7oCYHKTqTpLgtlSsMJfpQG3veTrk+9DoAldClDT1K9ux3ecK7RCt/k710UbKZaxDrLNevXFMTnyDOPDD3+l/G9fMKy6HrAqM4FtclF93b1Jb1eTK+MFD1ShTpurHMQwuHcfrfQ9H2J0CpgTVpcZ2MTTskP/Rg5uN0xVI7Q4P4PfsrC9029pWNc8WPR0dDkfg+vyhHsHZ4ZS+scmvj7Vhw3N19/b6bIEKMJOHZfBrMf9/n0Vmvan7A2aPYPDM7rdap3BzhdN7oum6KElqHeQA+4i4KeXoVKLkoJms4EMfYpjYutbRPoMc1cuxEAM2ZnjpJiSvzbuvwxbydVTHfxd2k/YudDUBaG1XgIEE7qYzKAudvIc/nIKmqNhoW5TLaj0z/tE/LdG6439W4r4EQNqsrnzi8F+SRxwbUad3zw5UwBsBpq170yS8x42nmSDu99sR9UV9DCbbn1P/B4tvxViIfwtNGFgwMDgl8flF360sPtNyB9GGuKu8I460tuyRuWXSt6+ELP/g66MpEUbNE3LOLdOCuOWdlEjNsJi+TyPyGxpPSyIQEqiLUX4GfhtcJfT9LUJltxKkxmK6m6p1MQE53/EBHJicqAKVLZawtNZIIQtWiV2SJPmSd4O2YOkiv7r0jAEzPuuNqL8Dl9WTdEgr6ckF41R5KMZMlJvDBXWxVVj4mnjkBDyOHdmp6x9X5GRGeXG9NztHe1/haxJir4OMAo3zWE2BWvZTwtgOWeCpSn515uDveIxsfjxmpGk4RHuGWkwQBl9oX2Vj0jPQE X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c32978ae-40cb-4e11-9511-08dbf4e35135 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2023 16:08:56.2185 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8t3aJfPrbmn8FfH2xo75WxxLD+Lo+LVezPPFLy1vSyc30UmkxqZu/8Mcjp84cL76cntvldwz5zIenhRl37f0Bw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB8057 Add suspend/resume support for Layerscape LS1021a. In the suspend path, PME_Turn_Off message is sent to the endpoint to transition the link to L2/L3_Ready state. In this SoC, there is no way to check if the controller has received the PME_To_Ack from the endpoint or not. So to be on the safer side, the driver just waits for PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3 state depending on the VAUX supply. In the resume path, the link is brought back from L2 to L0 by doing a software reset. Acked-by: Roy Zang Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Notes: Change from v5 to v6 - remove reduntant pci->pp.ops = &ls_pcie_host_ops; Change from v4 to v5 - update comit message - remove a empty line - use comments /* Reset the PEX wrapper to bring the link out of L2 */ - pci->pp.ops = pcie->drvdata->ops, ls_pcie_host_ops to the "ops" member of layerscape_drvdata. - don't set pcie->scfg = NULL at error path Change from v3 to v4 - update commit message. - it is reset a glue logic part for PCI controller. - use regmap_write_bits() to reduce code change. Change from v2 to v3 - update according to mani's feedback change from v1 to v2 - change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 83 ++++++++++++++++++++- 1 file changed, 80 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index aea89926bcc4f..711563777aeba 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -35,11 +35,19 @@ #define PF_MCR_PTOMR BIT(0) #define PF_MCR_EXL2S BIT(1) +/* LS1021A PEXn PM Write Control Register */ +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) +#define PMXMTTURNOFF BIT(31) +#define SCFG_PEXSFTRSTCR 0x190 +#define PEXSR(idx) BIT(idx) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { const u32 pf_off; + const struct dw_pcie_host_ops *ops; int (*exit_from_l2)(struct dw_pcie_rp *pp); + bool scfg_support; bool pm_support; }; @@ -47,6 +55,8 @@ struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; void __iomem *pf_base; + struct regmap *scfg; + int index; bool big_endian; }; @@ -171,18 +181,70 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) return 0; } +static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask) +{ + /* Send PME_Turn_Off message */ + regmap_write_bits(scfg, reg, mask, mask); + + /* + * There is no specific register to check for PME_To_Ack from endpoint. + * So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US. + */ + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); + + /* + * Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit + * to complete the PME_Turn_Off handshake. + */ + regmap_write_bits(scfg, reg, mask, 0); +} + +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF); +} + +static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask) +{ + /* Reset the PEX wrapper to bring the link out of L2 */ + regmap_write_bits(scfg, reg, mask, mask); + regmap_write_bits(scfg, reg, mask, 0); + + return 0; +} + +static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, }; +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { + .host_init = ls_pcie_host_init, + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, +}; + static const struct ls_pcie_drvdata ls1021a_drvdata = { - .pm_support = false, + .pm_support = true, + .scfg_support = true, + .ops = &ls1021a_pcie_host_ops, + .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, + .ops = &ls_pcie_host_ops, .exit_from_l2 = ls_pcie_exit_from_l2, }; @@ -205,6 +267,8 @@ static int ls_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct ls_pcie *pcie; struct resource *dbi_base; + u32 index[2]; + int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -217,9 +281,8 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->drvdata = of_device_get_match_data(dev); pci->dev = dev; - pci->pp.ops = &ls_pcie_host_ops; - pcie->pci = pci; + pci->pp.ops = pcie->drvdata->ops; dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); @@ -230,6 +293,20 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + if (pcie->drvdata->scfg_support) { + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + dev_err(dev, "No syscfg phandle specified\n"); + return PTR_ERR(pcie->scfg); + } + + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); + if (ret) + return ret; + + pcie->index = index[1]; + } + if (!ls_pcie_is_bridge(pcie)) return -ENODEV;