From patchwork Wed Dec 6 15:58:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13481972 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="j5JbaDz0" Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2047.outbound.protection.outlook.com [40.107.21.47]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F4151112; Wed, 6 Dec 2023 07:59:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LoOCiGfM5zDpLcfBQAfSFttnjcFbatrAP7yEsJvXlUrFxUXBOSAcg1YmNqrsIlUaC8g8rFmcvbx9Bp4H+5hVJ7QpUbJ9aKQKanqb4lJEwwrhoISn3Cy8HuLiEPykYdpq+weyEFEv3rTVR9NlCWtRLnZBj8BtSXrmCAGUUaqRSQ2lEhjmjC7FEmM5zXJanyG9lwhw5H6qtU3Q3u8zs8U0ojoE81ig3Bre/gRQpyaBnDr83TClvcJ1HTzPSAMGeB4dHpNd2bfpPox38RjO8ZEen+XhzjNvu4ILnw5/QRF6gF49M4hD1VbVBwsmT2jDoJaU+h1XplkkmEIZWI0dyojw2Q== ARC-Message-Signature: i=1; a=rsa-sha256; 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b=j5JbaDz0tGEXPdUuGtjJdMLh/QPivwNcDu0cUFZT9UFsYd/DzU9yAPA64R85+DhNUUXhZUfUQHs/7c0GXTxAuj0zd4anKiQimMjzPv6I4+fc5IenHa/qvtFJJUogRU7lhgyJVecZ2YXs2FR1LK19WdsV763xaKjDSi+pq2UdRKE= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DB9PR04MB8123.eurprd04.prod.outlook.com (2603:10a6:10:243::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.24; Wed, 6 Dec 2023 15:59:38 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%6]) with mapi id 15.20.7068.022; Wed, 6 Dec 2023 15:59:38 +0000 From: Frank Li To: imx@lists.linux.dev, Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , linux-pci@vger.kernel.org (open list:PCI DRIVER FOR IMX6), linux-arm-kernel@lists.infradead.org (moderated list:PCI DRIVER FOR IMX6), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/9] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET Date: Wed, 6 Dec 2023 10:58:57 -0500 Message-Id: <20231206155903.566194-4-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231206155903.566194-1-Frank.Li@nxp.com> References: <20231206155903.566194-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR21CA0015.namprd21.prod.outlook.com (2603:10b6:a03:114::25) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB9PR04MB8123:EE_ X-MS-Office365-Filtering-Correlation-Id: 317e8671-5f9f-463b-ffbb-08dbf6745977 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QLBYNiMRniwrf2M2DG+NJrBTizBv+XxJ83zUfvWj9G6N8tslVAknPsDNGwoEqu9ml2jUXoH1BMf5Vow97Ok6ylWEYi5qPCMAbRoNuzuMFJIB8NJfOzL5oLFUdEu6vcZ5ZMeYPG0C+edLOkbKpp2wTvAlG5oNBkH+G4vFSKT647Iz9DFbB/yPBUQ627wHM8qlyRNxdsO9BAn4Xbrrs69eLwXS4J588sjgzhS9yrA96Y9PuK0lP8iOVChk1bpaTguxl5xzBh/c4j1CSl4e2EIbBNo7jDNMXTt63iGEqqBBfUzlTrPoL7Y68MKitB/xg4DSw+l/dk/nBWWLHhMHJxxDtjWLfIC5aFwUeW9nq72y31MUwnCoPiXDiLSRoD7xtWN0UHXTmy009Qu/y/lcE5mwzABcCLjdCyPd0cXFvkDBJA6MNAmaKpHXgW1pZgYm11KcBptFwGwTzsr4hJKNb7kNi9kXJftyApbYrROLY3Z6grSxPAQmFUt9uPq2UGB15qQECPZJufApT/1jpEyQpdrXwhHUI/YxtSskn8uu2vAXEbppKlzlJC8phK1zNqIsQQ8jojh63UK2vHc/JLVfCvY/MfnJxQQdlWT1dSSJoBmdw2rYJRBHbQEdOk2djbXRmQ59bScHCJ85ufpPyPfvgbJIYJB3D+gYxzaBrW03VSkn8jwS8UKz1Gigt9TspORsTBivLkNOQfjW8kjFnNhG412SbYHnOAtk5G21Ey99g5w1BBumyzpZNmdGKSziSyjTF00zAfVUoGauAapx+FoNNEOEBv4Q33Oq7cmN4cqM4FzKmXv1wsM1Fy+iA4dZHz671RroPtB7ZpWAMNaToQc6N7jj9es8tElzpOw3bWZHsqFphBrPfw1SWFwrGjKq8AZ9BwN5r3t6qYqhUJeZUillmUAL1wxwaRsGhDigjjAibsPhxeAkKstZ+HPy5w5KOfs+wO0Z0rxXN/hBYkeUpjG2jGS7Q9nAaMb3FqpK+gBAkQtCvVRgo+AxhHginzf7BQNNDjLxaIvWhUFSQwjlcgAkJBNQnLsxHT0nh+1sfy+Yvowu9LQS6GA0fN5ioGcdgt76Uo6yTKNYouOEZA90hEo4w8koN8jEBkLyLnnCK8bc6BjwgM10zGVMU9JlQzAT8L84Zau9HPn24X8/rDAljSshQqbpRkfkgtFD1+sTTWf8RRBIThCsgNuUeidPxeZqEGo936hsp18ZfhjIhxOx3rCcQBkojCuFqnTwkgnJG1JgvU0JKsyl+Vh4OCdb0W7DoQw50CO/TZYKx9hbxYNcvzANYXYsAJV6YyQZAb1nNtxibsl8xi1rXXhfrY7REguA6gq8tuARpOZVXYojEPOlZoiEong3LNz751hWrFYcXQgYIjk4l/Lg2z26SApse7TzRQSmbWW+s+RWTfUBBi4LbNCc1vT5PqBMC05eVD+0QWOxDarMvubKas3QFlC5gBSoBz89YGgd/5I+JJCUKk7f2pZRA/A8Br82fbOecJLkCZTFPLabZ+4sSUtaxWauBf25AUoghtlst+M66FZBjSwqTE7jtfkZ3V/GVg3wLzWRazgpRLg+MsQ= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 317e8671-5f9f-463b-ffbb-08dbf6745977 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2023 15:59:38.2579 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LzgIQoBLCGaoN008vJxYV7NXGYgkSRTjQ5vQRWkCabivXEc0DVA/duoEzXBql45fJ6gKq9DFkJ8FB5lUeN7cEg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8123 Refactors the reset handling logic in the imx6 PCI driver by adding IMX6_PCIE_FLAG_HAS_*_RESET bitmask define for drvdata::flags. The drvdata::flags and a bitmask ensures a cleaner and more scalable switch-case structure for handling reset. Signed-off-by: Frank Li Reviewed-by: Philipp Zabel --- drivers/pci/controller/dwc/pci-imx6.c | 115 +++++++++++--------------- 1 file changed, 47 insertions(+), 68 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index bcf52aa86462..62d77fabd82a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -63,6 +63,8 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_HAS_CLK_INBOUND_AXI BIT(3) #define IMX6_PCIE_FLAG_HAS_CLK_AUX BIT(4) #define IMX6_PCIE_FLAG_HAS_PHY BIT(5) +#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(6) +#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(7) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -696,18 +698,13 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { - switch (imx6_pcie->drvdata->variant) { - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) reset_control_assert(imx6_pcie->pciephy_reset); - fallthrough; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: + + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) reset_control_assert(imx6_pcie->apps_reset); - break; + + switch (imx6_pcie->drvdata->variant) { case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, @@ -728,6 +725,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; + default: + break; } /* Some boards don't have PCIe reset GPIO. */ @@ -741,14 +740,11 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) struct dw_pcie *pci = imx6_pcie->pci; struct device *dev = pci->dev; - switch (imx6_pcie->drvdata->variant) { - case IMX8MQ: - case IMX8MQ_EP: - reset_control_deassert(imx6_pcie->pciephy_reset); - break; - case IMX7D: + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) reset_control_deassert(imx6_pcie->pciephy_reset); + switch (imx6_pcie->drvdata->variant) { + case IMX7D: /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle * Corrector" and other mysterious undocumented things. @@ -780,11 +776,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) usleep_range(200, 500); break; - case IMX6Q: /* Nothing to do */ - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: + default: break; } @@ -831,16 +823,12 @@ static void imx6_pcie_ltssm_enable(struct device *dev) IMX6Q_GPR12_PCIE_CTL_2, IMX6Q_GPR12_PCIE_CTL_2); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_deassert(imx6_pcie->apps_reset); + default: break; } + + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) + reset_control_deassert(imx6_pcie->apps_reset); } static void imx6_pcie_ltssm_disable(struct device *dev) @@ -854,16 +842,12 @@ static void imx6_pcie_ltssm_disable(struct device *dev) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0); break; - case IMX7D: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - reset_control_assert(imx6_pcie->apps_reset); + default: break; } + + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) + reset_control_assert(imx6_pcie->apps_reset); } static int imx6_pcie_start_link(struct dw_pcie *pci) @@ -1335,36 +1319,24 @@ static int imx6_pcie_probe(struct platform_device *pdev) "failed to get pcie phy\n"); } - switch (imx6_pcie->drvdata->variant) { - case IMX7D: - if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; - - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, - "pciephy"); - if (IS_ERR(imx6_pcie->pciephy_reset)) { - dev_err(dev, "Failed to get PCIEPHY reset control\n"); - return PTR_ERR(imx6_pcie->pciephy_reset); - } - - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); - if (IS_ERR(imx6_pcie->apps_reset)) { - dev_err(dev, "Failed to get PCIE APPS reset control\n"); - return PTR_ERR(imx6_pcie->apps_reset); - } - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MP: - case IMX8MP_EP: - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, - "apps"); + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { + imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); if (IS_ERR(imx6_pcie->apps_reset)) return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), "failed to get pcie apps reset control\n"); + } - break; + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { + imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx6_pcie->pciephy_reset)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), + "Failed to get PCIEPHY reset control\n"); + } + + switch (imx6_pcie->drvdata->variant) { + case IMX7D: + if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) + imx6_pcie->controller_id = 1; default: break; } @@ -1492,32 +1464,39 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX7D] = { .variant = IMX7D, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", }, [IMX8MQ] = { .variant = IMX8MQ, - .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX, + .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX | + IMX6_PCIE_FLAG_HAS_APP_RESET | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", }, [IMX8MM] = { .variant = IMX8MM, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | IMX6_PCIE_FLAG_HAS_CLK_AUX | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", }, [IMX8MP] = { .variant = IMX8MP, .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | IMX6_PCIE_FLAG_HAS_CLK_AUX | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, .flags = IMX6_PCIE_FLAG_HAS_CLK_AUX | - IMX6_PCIE_FLAG_HAS_PHY, + IMX6_PCIE_FLAG_HAS_PHY | + IMX6_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", },