From patchwork Mon Dec 18 03:04:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13496158 X-Patchwork-Delegate: bhelgaas@google.com Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA62B6FD1 for ; Mon, 18 Dec 2023 03:04:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1702868681-086e236fef3eca0001-0c9NHn Received: from ZXSHMBX3.zhaoxin.com (ZXSHMBX3.zhaoxin.com [10.28.252.165]) by mx1.zhaoxin.com with ESMTP id XgvtgcWm6OdhM7cr (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Mon, 18 Dec 2023 11:04:41 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from ZXBJMBX03.zhaoxin.com (10.29.252.7) by ZXSHMBX3.zhaoxin.com (10.28.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 18 Dec 2023 11:04:40 +0800 Received: from xin.lan (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 18 Dec 2023 11:04:37 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 From: LeoLiu-oc X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , , , , , , , , , , CC: , , , , LeoLiuoc Subject: [PATCH v2 3/3] PCI/ACPI: Add pci_acpi_program_hest_aer_params() Date: Mon, 18 Dec 2023 11:04:30 +0800 X-ASG-Orig-Subj: [PATCH v2 3/3] PCI/ACPI: Add pci_acpi_program_hest_aer_params() Message-ID: <20231218030430.783495-4-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218030430.783495-1-LeoLiu-oc@zhaoxin.com> References: <20231115091612.580685-1-LeoLiu-oc@zhaoxin.com> <20231218030430.783495-1-LeoLiu-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX3.zhaoxin.com[10.28.252.165] X-Barracuda-Start-Time: 1702868681 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 5014 X-Barracuda-BRTS-Status: 0 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.118228 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: LeoLiuoc Call the func pci_acpi_program_hest_aer_params() for every PCIe device, the purpose of this function is to extract register value from HEST PCIe AER structures and program them into AER Capabilities. Signed-off-by: LeoLiuoc --- drivers/pci/pci-acpi.c | 98 ++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 9 ++++ drivers/pci/probe.c | 1 + 3 files changed, 108 insertions(+) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 004575091596..3a183d5e20cb 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "pci.h" /* @@ -783,6 +784,103 @@ int pci_acpi_program_hp_params(struct pci_dev *dev) return -ENODEV; } +#ifdef CONFIG_ACPI_APEI +static void program_hest_aer_endpoint(struct acpi_hest_aer_common aer_endpoint, + struct pci_dev *dev, int pos) +{ + u32 uncor_mask; + u32 uncor_severity; + u32 cor_mask; + u32 adv_cap; + + uncor_mask = aer_endpoint.uncorrectable_mask; + uncor_severity = aer_endpoint.uncorrectable_severity; + cor_mask = aer_endpoint.correctable_mask; + adv_cap = aer_endpoint.advanced_capabilities; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, uncor_mask); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, uncor_severity); + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, cor_mask); + pci_write_config_dword(dev, pos + PCI_ERR_CAP, adv_cap); +} + +static void program_hest_aer_root(struct acpi_hest_aer_root *aer_root, struct pci_dev *dev, int pos) +{ + u32 root_err_cmd; + + root_err_cmd = aer_root->root_error_command; + + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, root_err_cmd); +} + +static void program_hest_aer_bridge(struct acpi_hest_aer_bridge *hest_aer_bridge, + struct pci_dev *dev, int pos) +{ + u32 uncor_mask2; + u32 uncor_severity2; + u32 adv_cap2; + + uncor_mask2 = hest_aer_bridge->uncorrectable_mask2; + uncor_severity2 = hest_aer_bridge->uncorrectable_severity2; + adv_cap2 = hest_aer_bridge->advanced_capabilities2; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK2, uncor_mask2); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER2, uncor_severity2); + pci_write_config_dword(dev, pos + PCI_ERR_CAP2, adv_cap2); +} + +static void program_hest_aer_params(struct hest_parse_aer_info info) +{ + struct pci_dev *dev; + int port_type; + int pos; + struct acpi_hest_aer_root *hest_aer_root; + struct acpi_hest_aer *hest_aer_endpoint; + struct acpi_hest_aer_bridge *hest_aer_bridge; + + dev = info.pci_dev; + port_type = pci_pcie_type(dev); + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); + if (!pos) + return; + + switch (port_type) { + case PCI_EXP_TYPE_ROOT_PORT: + hest_aer_root = info.hest_aer_root_port; + program_hest_aer_endpoint(hest_aer_root->aer, dev, pos); + program_hest_aer_root(hest_aer_root, dev, pos); + break; + case PCI_EXP_TYPE_ENDPOINT: + hest_aer_endpoint = info.hest_aer_endpoint; + program_hest_aer_endpoint(hest_aer_endpoint->aer, dev, pos); + break; + case PCI_EXP_TYPE_PCI_BRIDGE: + case PCI_EXP_TYPE_PCIE_BRIDGE: + hest_aer_bridge = info.hest_aer_bridge; + program_hest_aer_endpoint(hest_aer_bridge->aer, dev, pos); + program_hest_aer_bridge(hest_aer_bridge, dev, pos); + break; + default: + return; + } +} + +int pci_acpi_program_hest_aer_params(struct pci_dev *dev) +{ + struct hest_parse_aer_info info = { + .pci_dev = dev + }; + + if (!pci_is_pcie(dev)) + return -ENODEV; + + if (apei_hest_parse(hest_parse_pcie_aer, &info) == 1) + program_hest_aer_params(info); + + return 0; +} +#endif + /** * pciehp_is_native - Check whether a hotplug port is handled by the OS * @bridge: Hotplug port to check diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 5ecbcf041179..1fc28f7a5972 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -714,6 +714,15 @@ static inline void pci_save_aer_state(struct pci_dev *dev) { } static inline void pci_restore_aer_state(struct pci_dev *dev) { } #endif +#ifdef CONFIG_ACPI_APEI +int pci_acpi_program_hest_aer_params(struct pci_dev *dev); +#else +static inline int pci_acpi_program_hest_aer_params(struct pci_dev *dev) +{ + return 0; +} +#endif + #ifdef CONFIG_ACPI int pci_acpi_program_hp_params(struct pci_dev *dev); extern const struct attribute_group pci_dev_acpi_attr_group; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index ed6b7f48736a..45a45ab72846 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2274,6 +2274,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_serr(dev); pci_acpi_program_hp_params(dev); + pci_acpi_program_hest_aer_params(dev); } static void pci_release_capabilities(struct pci_dev *dev)