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Mon, 8 Jan 2024 11:06:46 +0000 Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::e6aa:baea:fd8c:4cd2]) by SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::e6aa:baea:fd8c:4cd2%7]) with mapi id 15.20.7135.032; Mon, 8 Jan 2024 11:06:46 +0000 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Daire McNamara , Emil Renner Berthing , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v14 12/22] PCI: microchip: Add request_event_irq() callback function Date: Mon, 8 Jan 2024 19:06:02 +0800 Message-Id: <20240108110612.19048-13-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240108110612.19048-1-minda.chen@starfivetech.com> References: <20240108110612.19048-1-minda.chen@starfivetech.com> X-ClientProxiedBy: ZQ0PR01CA0014.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:5::19) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_|SHXPR01MB0797:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b70f64c-6715-4a11-0958-08dc1039e740 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5AmbcUv6nEMSnQ0O+Pw37Eh8xmxjRg/bJXknrRSxiUf5CCK/gBIO4C4ufU6RbmvfedzaO49dbhhFoAfkak1gl62DgFnWt8e2M5IEkbLQoyGycsmSoRthK74igmhK9s/jg8HXVXXwKFV0aj0vHenduj5g731j2WhLMRNaz98T2ac4v8F2seGwA3tAFhq0mvjCh2tck+/Slr3hSt6TW6+OmHPX6TGmgTeJu24nNC3X5hAEdVnvLbLw6DTr7K5pUGT4vTl0d4+FDyGgPeR/cmJ6VrwfLvs7w51Y4y8Ug4O96o7EOCSAW2P6h9Ukizt5mXQ602aVduO1KIO2wullWcbaY6G5lKptHEYdr45SedHv22fdgjSdqtXUPfb6WfCzYYLVNnAztOdAtQ6HdJ5zx6L3pOQijhIif7kL5MWpaM1jgWD/VuZGtiWTUL2ttcN6QvineU1ZPrmBe4+hELiBe2wjvZExeVFhb8B8DsDLJM5DDiaz+rxngv2fhEYPIkXt5S1/tTpamOw0C+1Z0BCCMliNPpUPHWWf5Gg7oSPW1RUzdHhLmp/QgxpWvipxC3SF13ntOt/Fwph6r7I07gwrjokrqay33IYpsqLlzs03/IRNJ/nMUXZgluUCxlkaqg4qUjndC9N8r09xhYP212+LttjjmiDZ0z1FkFBK7ge0fcYSSiOa3zNBLjUgyOmxqAAwVtVFv4eQ2ZEf9HtQra1JRmRO+9sVVojolAs1mMPYIiY8aOMXOV0e8JSd3BxVHnjPpEaylGb1CAoOjLj+vGamVmH7aWDDDpCCpmzhOLUNj7tMhFx5EfAd2B1BLLxW1SiXV60MaXWij1LBn/Pu5QsW8cPGdDvHpF6+sA5a345UEyZ35BD9CbHpwrzsv+MDFlK+R2rmTOhR8/jglM3l75DZ5Lev53XfJ7C+ZPntpIL9WALWxkvv0QgyFLw0sOsz0zUJqQdczixIVbl/rPmp00HlWvgRUnPs5tKf3+0GFoajFm+5ZSm57Na4luLpdPv20l41ff2weJdrcvJVuXhU+S+4MZQnlHvIiCRE94enitl1/bR/2AqkuWkua3C9gfsD4QYELqHRDyM9/WhrXUeK53qKfzGx4INFhuwxYMDpRQdQWkLaj1UJunrxY/6OFSf9ObYpqwfRCwxJx5DMV4UFf6G6u74rCKRJOwLb3GY+MyBKLUcei72DnyLRwAWA7T/cLZ7SqhTucAgyF+QI1Mwh3gnugfIysDb+/7tRIz9eRlHrjncnOEhHc0W9361CV26Vvi1p6ttk3o4icLbHcmKhFIeFsPi1y0UjqTInL5AamPuZ2GGvHMJrgWZKG9bZQwkI2TU2bx3UrV3COz+OmsbhThCe4tgmQVtn4sheQ/0oS7kj97+URsgj06VBKZtmqyIvZzGZNWXzHoShLLTLIgKecFbrQ23eQ++B5hAHTQ5RCXDhJ6v4/grgsFMAq3L8ejKephnkRdwlnqjdaRe7g5KXy7ijtHWvS3AwA6RP/R+Tz36XMRVd75MPPVdVe7lH+zOQ/YQgoeTG+glJxVDtfAYwWvVZvMZUq39gX8YdUfffeonM7r6sx/vvg7rFmFhGw/aJ41GKcHYo2Hl6R19L+rFDgLcpVbwHtw== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1b70f64c-6715-4a11-0958-08dc1039e740 X-MS-Exchange-CrossTenant-AuthSource: SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2024 11:06:46.0278 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cGfH8itZEs1gYQ8LbGuOL/Pi9viMeY80lx0ABocOhbgc78oSRf3wUn9i+pq7+2aYcawf+4vItxeykxENUzMFnD2v7ZYD/5ATz5iYKhR6DCQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0797 As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt controller. Microchip Polarfire PCIe add some PCIe interrupts base on PLDA IP interrupt controller. Microchip Polarfire PCIe additional intrerrupts: EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR .... Both codes of register interrupts and mc_event_handler() contain additional interrupts symbol names, these can not be re-used. So add a new plda_event_handler() functions, which implements PLDA interrupt defalt handler. Add request_event_irq() callback function to compat Microchip Polorfire PCIe additional interrupts. Signed-off-by: Minda Chen Acked-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 31 ++++++++++++++++--- drivers/pci/controller/plda/pcie-plda.h | 5 +++ 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 0a5cd8b214cd..bf5ce33ee275 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -642,6 +642,11 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } +static irqreturn_t plda_event_handler(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + static void plda_handle_event(struct irq_desc *desc) { struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); @@ -803,6 +808,17 @@ static int mc_pcie_init_clks(struct device *dev) return 0; } +static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, + int event) +{ + return devm_request_irq(plda->dev, event_irq, mc_event_handler, + 0, event_cause[event].sym, plda); +} + +static const struct plda_event mc_event = { + .request_event_irq = mc_request_event_irq, +}; + static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) { struct device *dev = port->dev; @@ -904,7 +920,9 @@ static void mc_disable_interrupts(struct mc_pcie *port) writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); } -static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) +static int plda_init_interrupts(struct platform_device *pdev, + struct plda_pcie_rp *port, + const struct plda_event *event) { struct device *dev = &pdev->dev; int irq; @@ -928,8 +946,13 @@ static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_r return -ENXIO; } - ret = devm_request_irq(dev, event_irq, mc_event_handler, - 0, event_cause[i].sym, port); + if (event->request_event_irq) + ret = event->request_event_irq(port, event_irq, i); + else + ret = devm_request_irq(dev, event_irq, + plda_event_handler, + 0, NULL, port); + if (ret) { dev_err(dev, "failed to request IRQ %d\n", event_irq); return ret; @@ -983,7 +1006,7 @@ static int mc_platform_init(struct pci_config_window *cfg) return ret; /* Address translation is up; safe to enable interrupts */ - ret = plda_init_interrupts(pdev, &port->plda); + ret = plda_init_interrupts(pdev, &port->plda, &mc_event); if (ret) return ret; diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index adfca9f28458..16b81b23c213 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -127,6 +127,11 @@ struct plda_pcie_rp { int num_events; }; +struct plda_event { + int (*request_event_irq)(struct plda_pcie_rp *pcie, + int event_irq, int event); +}; + void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, size_t size);