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Mon, 29 Jan 2024 01:01:08 +0000 Received: from BJXPR01MB0855.CHNPR01.prod.partner.outlook.cn ([fe80::1ea1:19d5:efef:6fc6]) by BJXPR01MB0855.CHNPR01.prod.partner.outlook.cn ([fe80::1ea1:19d5:efef:6fc6%4]) with mapi id 15.20.7228.029; Mon, 29 Jan 2024 01:01:08 +0000 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Thomas Gleixner , Daire McNamara , Emil Renner Berthing , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v14,RESEND 15/22] PCI: microchip: Add event irqchip field to host port and add PLDA irqchip Date: Mon, 29 Jan 2024 09:00:59 +0800 Message-Id: <20240129010059.3672-2-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240129010059.3672-1-minda.chen@starfivetech.com> References: <20240129010059.3672-1-minda.chen@starfivetech.com> X-ClientProxiedBy: SHXPR01CA0016.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::25) To BJXPR01MB0855.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:18::12) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BJXPR01MB0855:EE_ X-MS-Office365-Filtering-Correlation-Id: 97d1dd78-fd7a-4791-603d-08dc2065c6d3 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: liJfsC6IQh3Je/RiSly5rUntpxz/OmRVmcf3d6w1O+xNu7r1mshknfYxv7ssoJjTnknT/PQ5y3h3v2RMUc7HXH3KnWmooP2sGt8JFsz3TCQG6X/ZSK41RABr2zTdPpxem40Jc1Fg3aGnekE3v4ji0sMldsBCahMP2z8dNE+5VY38V3ZeqhvuIgf4E04q1GhsCHdYVL3W+aB7Ta8OtEqS7G5Pkao5kpWrGeruz/b+cHCNHsgUF0VngJMUKGIRuFU4sFZp07g88fYNzL8RkEI7Znxh3NCdKYykfAwbbE6eSyylcaco9DUnvYgfwgJWGeLlfH6OdbM1xzBL8wvEQljHKe4pjIu2tBYgpakHnqHHiU6bqUdenq6pqm9w8VDTY5ywn06HMVFagKUnLtIGqqUSBZIPPFh0kDknIdEOlsQRMarnpDMHdn4UNRXpUynROFZofRtJ4znYwGUPI98SJItPK44Xx878fR1EIvmETHqSejhx4LptdIeSmsqvxBd1m1gFk2uwdJph10hF4eV9/cOZZgx1EnCneG6MTVUV3fgkJdCsrkaJgRm8cQIy3Qvb/pfq8DExNGCx34Ye/UYlk6yv8cjsPFRD0cTXe8QyWdqWqBLMOlaTjYluzDZONVZWKuHfD1RqQNMyBODE2IRpjK85skbnPUxUjLz5VmBp1QbdyJ3K1KkzaQztUU+wgFbauuGWCacEImqbpg7TORxvmYJbwQdk+pVO+dVGY3OfuFBn3NFq6fKbLFtPn7dmLUzaeN4WIN9w6UVZmjkNjYH7KtXb3xu2KnVrzDH+tgJ5DQX6XP2XKbzxa3PMAqAlujLmqbg0BSQTo7Ps6d0liNDdCuSa3L+2JFXcD8/aRbb1ZhjAceSuwt0GBp4NHTn/j+vOGWvkor22/fyc4kR+bBnXUJSbLv4oXUmTwuDtHqJWhoYFF6ROS/6LTPVWukEkcRQaAdOffEo5h2pccV6yhBAIt7Q7kb1/vzH2ii7YafimC8tEm11pSc+/03gmj/wbVN+Z0vsQUIoJfbnTkTKgDFYySvpqOJqs4u9JOTIK7hft3qILsWcqTaCDAckRdTnC6RZg3g7K8Yx2Npc5w1hV/2kMBQ3Jf8s9rccFh+eS5dM2x3BZgBb83W3kvBVDSNr+UQrpmtD1iGBTSA+ukFzU9sm/RBcLqNp53/AsjtK7u+NhiY4QOvkiJZ8Jt28zLprkJvTyAmylRToe0ZUhcYvDBqP4oEhqrcRwNbdKOgcKDjNHKKqSpDl7ySYz+mFrv/9E1fB8mNicJL2su7ZV0rTrx3uP+j4kw3bV0qjwiW7Xkwmp+B6q+lbtqsrZi72y3Axh/0K2ne9cLQXC6B9kHpHRw0gPhlMx2N4czOal4BIdy+vjJA9EiSjfHYjHHnsoW5FgBt7Xj/yMI+p5eM3MCbNT6dQ3QBLvoYwqb9WCLqNYuzGPdKPBmVg92DDxaeFAz9CjtEmgJ+p1Kh3//CcXFunp67VzaUncYAclOrNS6iAaV/jAraJODJsRmxyc1+xUs+wft+WEYQweor+vJ8zRX/9syKZONwtTmvgLltfOW88QOydLkWi2wrq+wkTZZDN64e/PM9o/9e5oVR9Y2bf0v+HIJ0x4gFLUIg== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 97d1dd78-fd7a-4791-603d-08dc2065c6d3 X-MS-Exchange-CrossTenant-AuthSource: BJXPR01MB0855.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2024 01:01:08.0035 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: CKy62uAlQ3tnUSqv0Zx9c629DvVbOzttP2+pApfb5ekqTcB5GwyElE10h7e/ho7kae30Lf08AFT9Zpin/ewKCSi/ufkhg3nyirlDc91SIq4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BJXPR01MB0855 As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt controller. Microchip PolarFire PCIE event IRQs includes PLDA interrupts and Polarfire their own interrupts. The interrupt irqchip ops includes ack/mask/unmask interrupt ops, which will write correct registers. Microchip Polarfire PCIe additional interrupts require to write Polarfire SoC self-defined registers. So Microchip PCIe event irqchip ops can not be re-used. To support PLDA its own event IRQ process, implements PLDA irqchip ops and add event irqchip field to struct pcie_plda_rp. Signed-off-by: Minda Chen Acked-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++- drivers/pci/controller/plda/pcie-plda.h | 3 + 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index b3df373a2141..beaf5c27da84 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = { .irq_unmask = mc_unmask_event_irq, }; +static u32 plda_hwirq_to_mask(int hwirq) +{ + u32 mask; + + /* hwirq 23 - 0 are the same with register */ + if (hwirq < EVENT_PM_MSI_INT_INTX) + mask = BIT(hwirq); + else if (hwirq == EVENT_PM_MSI_INT_INTX) + mask = PM_MSI_INT_INTX_MASK; + else + mask = BIT(hwirq + PCI_NUM_INTX - 1); + + return mask; +} + +static void plda_ack_event_irq(struct irq_data *data) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + + writel_relaxed(plda_hwirq_to_mask(data->hwirq), + port->bridge_addr + ISTATUS_LOCAL); +} + +static void plda_mask_event_irq(struct irq_data *data) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + u32 mask, val; + + mask = plda_hwirq_to_mask(data->hwirq); + + raw_spin_lock(&port->lock); + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); + val &= ~mask; + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); + raw_spin_unlock(&port->lock); +} + +static void plda_unmask_event_irq(struct irq_data *data) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + u32 mask, val; + + mask = plda_hwirq_to_mask(data->hwirq); + + raw_spin_lock(&port->lock); + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); + val |= mask; + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); + raw_spin_unlock(&port->lock); +} + +static struct irq_chip plda_event_irq_chip = { + .name = "PLDA PCIe EVENT", + .irq_ack = plda_ack_event_irq, + .irq_mask = plda_mask_event_irq, + .irq_unmask = plda_unmask_event_irq, +}; + static const struct plda_event_ops plda_event_ops = { .get_events = plda_get_events, }; @@ -777,7 +835,9 @@ static const struct plda_event_ops plda_event_ops = { static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { - irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq); + struct plda_pcie_rp *port = (void *)domain->host_data; + + irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq); irq_set_chip_data(irq, domain->host_data); return 0; @@ -962,6 +1022,9 @@ static int plda_init_interrupts(struct platform_device *pdev, if (!port->event_ops) port->event_ops = &plda_event_ops; + if (!port->event_irq_chip) + port->event_irq_chip = &plda_event_irq_chip; + ret = plda_pcie_init_irq_domains(port); if (ret) { dev_err(dev, "failed creating IRQ domains\n"); @@ -1039,6 +1102,7 @@ static int mc_platform_init(struct pci_config_window *cfg) return ret; port->plda.event_ops = &mc_event_ops; + port->plda.event_irq_chip = &mc_event_irq_chip; /* Address translation is up; safe to enable interrupts */ ret = plda_init_interrupts(pdev, &port->plda, &mc_event); diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index e0e5e7cc8434..a3ce01735bea 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -107,6 +107,8 @@ enum plda_int_event { #define PLDA_NUM_DMA_EVENTS 16 +#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS + PLDA_INTX) +#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS + PLDA_MSI) #define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) /* @@ -155,6 +157,7 @@ struct plda_pcie_rp { raw_spinlock_t lock; struct plda_msi msi; const struct plda_event_ops *event_ops; + const struct irq_chip *event_irq_chip; void __iomem *bridge_addr; int num_events; };