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Tue, 30 Jan 2024 02:01:39 -0800 (PST) Received: from localhost.localdomain ([123.51.167.56]) by smtp.googlemail.com with ESMTPSA id sg14-20020a17090b520e00b00295bc312ceasm730672pjb.34.2024.01.30.02.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 02:01:39 -0800 (PST) From: Jian-Hong Pan To: Mika Westerberg , David Box , Damien Le Moal , Niklas Cassel , Nirmal Patel , Jonathan Derrick Cc: linux-ide@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux@endlessos.org, Jian-Hong Pan Subject: [PATCH 2/2] PCI: vmd: enable PCI PM's L1 substates of remapped PCIe port and NVMe Date: Tue, 30 Jan 2024 18:00:51 +0800 Message-ID: <20240130100050.14182-2-jhp@endlessos.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The remmapped PCIe port and NVMe have PCI PM L1 substates capability on ASUS B1400CEAE, but they are disabled originally: Capabilities: [900 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+ PortCommonModeRestoreTime=32us PortTPowerOnTime=10us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- T_CommonMode=0us LTR1.2_Threshold=0ns L1SubCtl2: T_PwrOn=10us Power on all of the VMD remapped PCI devices before enable PCI-PM L1 PM Substates by following "Section 5.5.4 of PCIe Base Spec Revision 5.0 Version 0.1". Then, PCI PM's L1 substates control are enabled accordingly. Link: https://bugzilla.kernel.org/show_bug.cgi?id=218394 Signed-off-by: Jian-Hong Pan --- drivers/pci/controller/vmd.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index 87b7856f375a..b1bbe8e6075a 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -738,6 +738,12 @@ static void vmd_copy_host_bridge_flags(struct pci_host_bridge *root_bridge, vmd_bridge->native_dpc = root_bridge->native_dpc; } +static int vmd_power_on_pci_device(struct pci_dev *pdev, void *userdata) +{ + pci_set_power_state(pdev, PCI_D0); + return 0; +} + /* * Enable ASPM and LTR settings on devices that aren't configured by BIOS. */ @@ -928,6 +934,13 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) vmd_acpi_begin(); pci_scan_child_bus(vmd->bus); + + /* + * Make PCI devices at D0 when enable PCI-PM L1 PM Substates from + * Section 5.5.4 of PCIe Base Spec Revision 5.0 Version 0.1 + */ + pci_walk_bus(vmd->bus, vmd_power_on_pci_device, NULL); + vmd_domain_reset(vmd); /* When Intel VMD is enabled, the OS does not discover the Root Ports