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Wed, 14 Feb 2024 00:48:47 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 14 Feb 2024 14:18:31 +0530 Subject: [PATCH v2] PCI: Add D3 support for PCI bridges in DT based platforms Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240214-pcie-qcom-bridge-v2-1-9dd6dbb1b817@linaro.org> X-B4-Tracking: v=1; b=H4sIAF5+zGUC/3WNQQ6CMBBFr0K6tmbaIgVX3sOwaMsAkyjF1hAN4 e4WdOFCl+9P3puZRQyEkR2zmQWcKJIfEshdxlxvhg45NYmZBJmDUIKPjpDfnL9yG6hJd1uUIE2 lNRjFkjYGbOmxJc914p7i3Yfn9mES6/qOSfgRmwQH3iLqStvWHkCfLjSY4Pc+dGv8Y8o/Zl40W pdVqQoH32a9LMsL2QkzsesAAAA= To: Bjorn Helgaas , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring Cc: Lukas Wunner , Mika Westerberg , quic_krichai@quicinc.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3621; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=TwT82vyqx3budLWaWyEGG1wI/RIEzRBWQO73BeFdsz4=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlzH5sGhjF7J1FtVOKJx9eRXLfbFkb5+6yag7MX OOkW60PAhyJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZcx+bAAKCRBVnxHm/pHO 9VuIB/98qb1C2T1l8XOGquybgU2brNTm+9pRP8Vxy5BH8+tiSMtGprtKXvWLjFtQPDdar3OgpL0 5qarp886xtZHtNGk9lOxayzaJG5tbD8KfHBvehbn469Qqg8s+vlW0qlDFLMPiPjd1Ek5uPU0BAK gpqf7A0dIMciJps7ig/5DS0rZWv8KXw0nXl6zPZhpOx+FVkHsw6QUb8AM1N52yg3aU9IsSRI3O+ NTfNw4WW8IyfPddqXUpM0kZZ2iflPZw2KSnRqj7e2h/iM+wrnaLoB+xuOu42m5L/fXoCUSvrSKk NOXPIhckauJNyaPkTwptDaLWAxiAnmmZhwrzlTClBzzMKdor X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Currently, PCI core will enable D3 support for PCI bridges only when the following conditions are met: 1. Platform is ACPI based 2. Thunderbolt controller is used 3. pcie_port_pm=force passed in cmdline While options 1 and 2 do not apply to most of the DT based platforms, option 3 will make the life harder for distro maintainers. Due to this, runtime PM is also not getting enabled for the bridges. To fix this, let's make use of the "supports-d3" property [1] in the bridge DT nodes to enable D3 support for the capable bridges. This will also allow the capable bridges to support runtime PM, thereby conserving power. Ideally, D3 support should be enabled by default for the more recent PCI bridges, but we do not have a sane way to detect them. [1] https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-pci-bridge.yaml#L31 Signed-off-by: Manivannan Sadhasivam --- This patch is tested on Qcom SM8450 based development board with an out-of-tree DT patch. NOTE: I will submit the DT patches adding this property for applicable bridges in Qcom SoCs separately. Changes in v2: - Switched to DT based approach as suggested by Lukas. - Link to v1: https://lore.kernel.org/r/20240202-pcie-qcom-bridge-v1-0-46d7789836c0@linaro.org --- drivers/pci/of.c | 12 ++++++++++++ drivers/pci/pci.c | 3 +++ drivers/pci/pci.h | 6 ++++++ 3 files changed, 21 insertions(+) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20240131-pcie-qcom-bridge-b6802a9770a3 Best regards, diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 51e3dd0ea5ab..77dc14a3c91d 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -786,3 +786,15 @@ u32 of_pci_get_slot_power_limit(struct device_node *node, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +/** + * of_pci_bridge_d3 - Check if the bridge is supporting D3 states or not + * + * @node: device tree node of the bridge + * + * Return: True if the bridge is supporting D3 states, False otherwise. + */ +bool of_pci_bridge_d3(struct device_node *node) +{ + return of_property_read_bool(node, "supports-d3"); +} diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d8f11a078924..3309c45b656c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1142,6 +1142,9 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev) if (pci_use_mid_pm()) return false; + if (dev->dev.of_node) + return of_pci_bridge_d3(dev->dev.of_node); + return acpi_pci_bridge_d3(dev); } diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2336a8d1edab..10387461b1fe 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -635,6 +635,7 @@ int of_pci_get_max_link_speed(struct device_node *node); u32 of_pci_get_slot_power_limit(struct device_node *node, u8 *slot_power_limit_value, u8 *slot_power_limit_scale); +bool of_pci_bridge_d3(struct device_node *node); int pci_set_of_node(struct pci_dev *dev); void pci_release_of_node(struct pci_dev *dev); void pci_set_bus_of_node(struct pci_bus *bus); @@ -673,6 +674,11 @@ of_pci_get_slot_power_limit(struct device_node *node, return 0; } +static inline bool of_pci_bridge_d3(struct device_node *node) +{ + return false; +} + static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } static inline void pci_release_of_node(struct pci_dev *dev) { } static inline void pci_set_bus_of_node(struct pci_bus *bus) { }