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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9DA.mail.protection.outlook.com (10.167.241.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7292.25 via Frontend Transport; Mon, 26 Feb 2024 06:02:15 +0000 Received: from aiemdee.2.ozlabs.ru (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 26 Feb 2024 00:02:13 -0600 From: Alexey Kardashevskiy To: CC: =?utf-8?q?Martin_Mare=C5=A1?= , Jonathan Cameron , Alexey Kardashevskiy Subject: [PATCH pciutils v2 2/2] lspci: Add TEE-IO extended capability bit Date: Mon, 26 Feb 2024 17:01:35 +1100 Message-ID: <20240226060135.3252162-3-aik@amd.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240226060135.3252162-1-aik@amd.com> References: <20240226060135.3252162-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DA:EE_|DM6PR12MB4331:EE_ X-MS-Office365-Filtering-Correlation-Id: e895ce99-eeda-451f-7864-08dc36907b71 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Alexey Kardashevskiy --- Changes: v2: * added the section number to the commit log --- lib/header.h | 1 + ls-caps.c | 1 + 2 files changed, 2 insertions(+) diff --git a/lib/header.h b/lib/header.h index 68cb3c1..0b0ed9a 100644 --- a/lib/header.h +++ b/lib/header.h @@ -777,6 +777,7 @@ #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ #define PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */ +#define PCI_EXP_DEVCAP_TEE_IO 0x40000000 /* TEE-IO Supported (TDISP) */ #define PCI_EXP_DEVCTL 0x8 /* Device Control */ #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ diff --git a/ls-caps.c b/ls-caps.c index 2c99812..65e92e6 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -717,6 +717,7 @@ static void cap_express_dev(struct device *d, int where, int type) printf(" SlotPowerLimit "); show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26); } + printf(" TEE-IO%c", FLAG(t, PCI_EXP_DEVCAP_TEE_IO)); printf("\n"); w = get_conf_word(d, where + PCI_EXP_DEVCTL);