From patchwork Sat Mar 30 04:19:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13611467 X-Patchwork-Delegate: manivannanece23@gmail.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF70A8467; Sat, 30 Mar 2024 04:20:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711772415; cv=none; b=MW07eQ7MppbwzPdR2hmzigUeM4j2m7hfLTvCxoi6coQ32Ma7e5bHUzJ8X4ABosPJruOk3GKw6mNMijxpX2MUtbm8hJ5ZqBQVVx5+dpSLA6YiCNlKaCNz1MHI2F0njLmUpbeZgvKh6YYtkk+RTRb/xqEZW2RU6tjKkPqbq25Y/uI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711772415; c=relaxed/simple; bh=ePPzqYfhVI3evLvbxbPEF1nIcYymLdbLe2OI//GAx8Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aKFsvnNCHER3ZVwuELWA7p58mel4loPOIxBZ+Hr08Rkl/g3QoD1Nt8VVzNduRp7y2bbun2OgG3Vol9xamECAjOEg+/OukMtH62asdrJhe0ha6hnhIRgPpYjySqH081HFjUr49u12JIqWYWfZ7nQCY4Xpt7d7+ja4RvDTu6e0s9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mETdyotD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mETdyotD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9C6B1C433B1; Sat, 30 Mar 2024 04:20:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711772415; bh=ePPzqYfhVI3evLvbxbPEF1nIcYymLdbLe2OI//GAx8Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mETdyotDE/i00ByKUZ/fO/c8pggRC43P1JerJeROWTNuNvCblnelcKHM9D2ZiDc9l wO7IFWiKB5TPNDJz0YO0WQxAx6xZmBWI9mBvLxbAjpHrWsWP4p3AE7T37T2dLE/jBc 2olUSDa+xHJGno0TajPvh/E4LVgESnhfmHJXbXZQwPQmyWHi3iiwv3o0lzrII15n5z n+Pajs/4wRqNuMApz4rItRteh025LY071SrEq/jE3fSGuNU4nsl9FA1jVZYc9MSOgI FRDqkJPExT6Cov4xBfnjRjHeQV9EPqbLqbAR8HIf4W+mr527dx7NehJ4b3y52mRtJ0 v2j96h1724b5Q== From: Damien Le Moal To: Manivannan Sadhasivam , Lorenzo Pieralisi , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Rick Wertenbroek , Wilfred Mallawa , Niklas Cassel Subject: [PATCH v2 14/18] PCI: rockchip-ep: Refactor endpoint link training enable Date: Sat, 30 Mar 2024 13:19:24 +0900 Message-ID: <20240330041928.1555578-15-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240330041928.1555578-1-dlemoal@kernel.org> References: <20240330041928.1555578-1-dlemoal@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The function rockchip_pcie_init_port() enables link training for a controller configured in EP mode. Enabling link training is again done in rockchip_pcie_ep_probe() after that function executed rockchip_pcie_init_port(). Enabling link training only needs to be done once, and doing so at the probe stage before the controller is actually started by the user serves no purpose. Refactor this by removing the link training enablement from both rockchip_pcie_init_port() and rockchip_pcie_ep_probe() and moving it to the endpoint start operation defined with rockchip_pcie_ep_start(). Enabling the controller configuration using the PCIE_CLIENT_CONF_ENABLE bit in the same PCIE_CLIENT_CONFIG register is also move to rockchip_pcie_ep_start() and both the controller configuration and link training enable bits are set with a single call to rockchip_pcie_write(). Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 14 ++++++-------- drivers/pci/controller/pcie-rockchip.c | 5 +++-- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index a7d008d95a8a..9215cac91f61 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -461,6 +461,12 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc) rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG); + /* Enable configuration and start link training */ + rockchip_pcie_write(rockchip, + PCIE_CLIENT_LINK_TRAIN_ENABLE | + PCIE_CLIENT_CONF_ENABLE, + PCIE_CLIENT_CONFIG); + return 0; } @@ -539,7 +545,6 @@ static int rockchip_pcie_ep_get_resources(struct rockchip_pcie_ep *ep) ep->ob_addr = devm_kcalloc(dev, ep->max_regions, sizeof(*ep->ob_addr), GFP_KERNEL); - if (!ep->ob_addr) return -ENOMEM; @@ -650,16 +655,9 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) rockchip_pcie_ep_hide_msix_cap(rockchip); - /* Establish the link automatically */ - rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, - PCIE_CLIENT_CONFIG); - /* Only enable function 0 by default */ rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); - rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, - PCIE_CLIENT_CONFIG); - return 0; err_release_resources: rockchip_pcie_ep_release_resources(ep); diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index 0ef2e622d36e..dbec700ba9f9 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -244,11 +244,12 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, PCIE_CLIENT_CONFIG); - regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | + regs = PCIE_CLIENT_ARI_ENABLE | PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); if (rockchip->is_rc) - regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; + regs |= PCIE_CLIENT_LINK_TRAIN_ENABLE | + PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; else regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP;