From patchwork Wed Apr 24 15:16:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13642011 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3253515EFC2; Wed, 24 Apr 2024 15:16:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713971816; cv=none; b=ez+hxNj15bmGeQ0C9NA9iQ7kM9oL1HxnvLqSwfj9JRXHly/jOxmd6EXzl+bzrUW3WNp4F6B+iJ5n85YaLvCIG98ORdP7BoR2/CaENVleUldlFrbS3p1SYhDH5h6k4DN/w/B2/AhgE7FMNYQa3rE2iS3akc1DTHZTBUuEKdB9yf0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713971816; c=relaxed/simple; bh=W5lkVQPb+eICdXIRorh9nge2BdMRIRVwedcZfqMZ7t0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hlcLau4rbuosWlYJccXN1m6edLrFVOtfGfMuXWUvkz4aFB/eQtu88AU+9Tv/m28FK1ovQKXPH5cF71VkRX/YOI+Y3VZivGXTRsjt2Sh/hQ7dr6rQimljDUuYEjFLe9YMeAz1i3ybuT5gtUiXe9MmWNLDYs8QwZkGXBse5crqn/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SqTO6HcD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SqTO6HcD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0D62AC2BBFC; Wed, 24 Apr 2024 15:16:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713971815; bh=W5lkVQPb+eICdXIRorh9nge2BdMRIRVwedcZfqMZ7t0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SqTO6HcDCupRkVmfvHYj/2vZpFJu0ljqCXrJLlwjwiCu4cYOf/wNcaMKpr2WgqEtS BWf5xc26z6yodbg7kg1xVn6wP6wW/LelNv3sNNbcqNUWmfxTC+ofawEHYx2HYQOxEq LGP/DSdIxZT8wJPAmIbFmTHSvxHVw2o1JrOYcaLJ5O4Bq0uI7YC9vVrEvo9I+go9aw jqhyyIHfcYDsptAdswYE8Wwe/cYo12QJN/sFzOnLdlrjeszQEElG9vnUFpYibzize6 hTJPVYxArOLBg9n1jvL7wVJPxarHmb2yESNqx+PumhrNl2RZrfHotp3ly6RF4ZJpIF nxl4goQv2Xzcg== From: Niklas Cassel Date: Wed, 24 Apr 2024 17:16:22 +0200 Subject: [PATCH 04/12] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240424-rockchip-pcie-ep-v1-v1-4-b1a02ddad650@kernel.org> References: <20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org> In-Reply-To: <20240424-rockchip-pcie-ep-v1-v1-0-b1a02ddad650@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6908; i=cassel@kernel.org; h=from:subject:message-id; bh=W5lkVQPb+eICdXIRorh9nge2BdMRIRVwedcZfqMZ7t0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNI0lYI+zc9b3KNhlaXB/Ybl3r9nTvo5Wye9iip5OoNPT PiR4S/tjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAExkyl9GhofqiYqBzuqC97Yd niH/9f6nZI/PNgdaqp5wOLy+3tmTt4rhf1zJUq4js57e+9UvKbJ3/rmzM9cYrvYMUU69c0R4le2 dSUwA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Document DT bindings for PCIe Endpoint controller found in Rockchip SoCs. Signed-off-by: Niklas Cassel --- .../bindings/pci/rockchip-dw-pcie-ep.yaml | 192 +++++++++++++++++++++ 1 file changed, 192 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml new file mode 100644 index 000000000000..57a6c542058f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe Endpoint controller on Rockchip SoCs + +maintainers: + - Niklas Cassel + +description: |+ + RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +properties: + compatible: + items: + - const: rockchip,rk3588-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: Data Bus Interface (DBI) shadow registers + - description: Rockchip designed configuration registers + - description: Memory region used to map remote RC address space + - description: Address Translation Unit (ATU) registers + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: apb + - const: addr_space + - const: atu + + clocks: + minItems: 6 + items: + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + - description: AHB clock for PCIe dbi + - description: APB clock for PCIe + - description: Auxiliary clock for PCIe + - description: PIPE clock + - description: Reference clock for PCIe + + clock-names: + minItems: 6 + items: + - const: aclk_mst + - const: aclk_slv + - const: aclk_dbi + - const: pclk + - const: aux + - const: pipe + - const: ref + + interrupts: + items: + - description: + Combined system interrupt, which is used to signal the following + interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, + hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, + edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app + - description: + Combined PM interrupt, which is used to signal the following + interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, + linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, + linkst_out_l0s, pm_dstate_update + - description: + Combined message interrupt, which is used to signal the following + interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, + pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active + - description: + Combined legacy interrupt, which is used to signal the following + interrupts - tx_inta, tx_intb, tx_intc, tx_intd + - description: + Combined error interrupt, which is used to signal the following + interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, + tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, + nf_err_rx, f_err_rx, radm_qoverflow + - description: + eDMA write channel 0 interrupt + - description: + eDMA write channel 1 interrupt + - description: + eDMA read channel 0 interrupt + - description: + eDMA read channel 1 interrupt + + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: pwr + - const: pipe + + vpcie3v3-supply: true + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - num-lanes + - phys + - phy-names + - power-domains + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + }; + }; +...