From patchwork Mon May 6 16:15:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 13655710 X-Patchwork-Delegate: kw@linux.com Received: from out-180.mta0.migadu.com (out-180.mta0.migadu.com [91.218.175.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEE8B156C69 for ; Mon, 6 May 2024 16:15:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715012133; cv=none; b=ZQV3IjRfM/bljcKzk/eHc02AYcpgM26UOIklZ3o1aud485ubq/fZzN2KiPcAau8EaVL0fBnbYoOh+EzUIs3VILidht4Yyagdnki9YF/Dhb1+jrgyABFWHSOfD2BiYbHlet7o+iYoeAV2eKRy1yGOinma7df2J6HCneLkufCBRpo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715012133; c=relaxed/simple; bh=ioA0HGN434X5LfI1Q/glCw84Ax+UD4cQobrMiTiDEoA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=m5KiDLUATfvklgoRet7pC3sAxMOEyCvfOCjFbL+V2J4SyrTn6CJ616QMBT9WDudmrZc6UQGN+rkw3nxYG4cCzaMhaAdU1uwRR3d7TTV3Sd1cUyf0wLQ4ELxsreedo5yv0d3X5x6eLfD/K1Lk6s3vM01Ta7APXFow4VpRZBj8tKI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=AGn0twPM; arc=none smtp.client-ip=91.218.175.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="AGn0twPM" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1715012130; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VQg5GnmyntnuTwJSymksMsk4lzmwO9PWXcLwJAirNTY=; b=AGn0twPM8mhmFzjce9Zg2phkoHLhsynNSoenjc+yvob6ogHFKyDXBJ5jm95zPqJV9dUG6C kwUGkz+9MaNPaQ4ZohphRJqe4u+HUmnSNLMd60Y9K89mdC00o9MT6zuFaxOer+NnVxX4K0 nkfkWmKUmv0kColXIUOYIIvPe2dpof8= From: Sean Anderson To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , linux-pci@vger.kernel.org Cc: Michal Simek , Bjorn Helgaas , Thippeswamy Havalige , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Anderson , stable@vger.kernel.org, Bharat Kumar Gogada Subject: [PATCH v2 2/7] PCI: xilinx-nwl: Fix off-by-one Date: Mon, 6 May 2024 12:15:05 -0400 Message-Id: <20240506161510.2841755-3-sean.anderson@linux.dev> In-Reply-To: <20240506161510.2841755-1-sean.anderson@linux.dev> References: <20240506161510.2841755-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT IRQs start at 0, so we don't need to subtract 1. Fixes: 9a181e1093af ("PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts") Cc: Signed-off-by: Sean Anderson --- (no changes since v1) drivers/pci/controller/pcie-xilinx-nwl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 0408f4d612b5..437927e3bcca 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -371,7 +371,7 @@ static void nwl_mask_intx_irq(struct irq_data *data) u32 mask; u32 val; - mask = 1 << (data->hwirq - 1); + mask = 1 << data->hwirq; raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); @@ -385,7 +385,7 @@ static void nwl_unmask_intx_irq(struct irq_data *data) u32 mask; u32 val; - mask = 1 << (data->hwirq - 1); + mask = 1 << data->hwirq; raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);