From patchwork Mon May 27 16:14:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 13675585 X-Patchwork-Delegate: bhelgaas@google.com Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 436C2169380; Mon, 27 May 2024 16:15:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.199 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716826517; cv=none; b=ieiG4MeiaJBlifaiaermQZQvFIoIWoZdtwhZrmKPK/oFHI0Jt+Clffahydjv6zRDkqK8Rl8d1piiJDEe0HbyHo05G695FHPrLpF5Me1XQej4PWY5U7b23cjJLbULqnrYZTi1BnS/HLDHaK2dwG20PYP5AnI90GtkOuvHGudddso= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716826517; c=relaxed/simple; bh=/RI6whJcmrvhiRO7t2XvDhnsZ9qXtW9I/fr2BpEIl5U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PhaVydLQEfWGLHpDNDoNaRcneuNbvo2PUXZoKRKJfmv4m56KP/tBMCLq0Ug8MhLSa1CfBXThL7Wb7rAaALcs14CSbeq5qpQGrpsZ1iXoadVmb+9oz1p5lBtAV/mpeZnrVMYTIzQPKmvtnly0xeTgJyeCHAbTek+yXSC1WTe3+jw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=E8RHx6bg; arc=none smtp.client-ip=217.70.183.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="E8RHx6bg" Received: by mail.gandi.net (Postfix) with ESMTPA id 3B155FF813; Mon, 27 May 2024 16:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1716826512; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1poOcFigCzvNGw/WIJa8uOgiTHrPvQYSCIrCvjonocA=; b=E8RHx6bg0cF5LcM53jS29vWdjSIUAfGgiMFIQZrgsLMstByXtH7NJXiQJ6+bi6+R8fMCEb 3rxCEVmRomYWYdekf/v32aXiE/9kFgvfZZep3JjemaR2oc9Oi9fbofn7AQ2icmXBD8eHBa GC0pb1A6DKk57ByjVD/13ZXC7MlTMtl4vacsij06M/vPt9WX1seXrUsX1Rc2QM2ixdJKyr 6APNKUol5ce/eZgE+gC8RriHVrTplJbCdCwowrgln8PDOmiFvzysRxa0EuWW5QEXI66ahi p3CmuamZHy+oEF510shOM2HKhNsX52WKDSYZGEQrVioInDz5S2hjQ8+m5Se/2Q== From: Herve Codina To: Simon Horman , Sai Krishna Gajula , Herve Codina , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lee Jones , Arnd Bergmann , Horatiu Vultur , UNGLinuxDriver@microchip.com, Andrew Lunn , Heiner Kallweit , Russell King , Saravana Kannan , Bjorn Helgaas , Philipp Zabel , Lars Povlsen , Steen Hegelund , Daniel Machon , Alexandre Belloni Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Allan Nielsen , Steen Hegelund , Luca Ceresoli , Thomas Petazzoni Subject: [PATCH v2 08/19] dt-bindings: interrupt-controller: Add support for Microchip LAN966x OIC Date: Mon, 27 May 2024 18:14:35 +0200 Message-ID: <20240527161450.326615-9-herve.codina@bootlin.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240527161450.326615-1-herve.codina@bootlin.com> References: <20240527161450.326615-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: herve.codina@bootlin.com The Microchip LAN966x outband interrupt controller (OIC) maps the internal interrupt sources of the LAN966x device to an external interrupt. When the LAN966x device is used as a PCI device, the external interrupt is routed to the PCI interrupt. Signed-off-by: Herve Codina Reviewed-by: Rob Herring (Arm) --- .../microchip,lan966x-oic.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml b/Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml new file mode 100644 index 000000000000..b2adc7174177 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/microchip,lan966x-oic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip LAN966x outband interrupt controller + +maintainers: + - Herve Codina + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: | + The Microchip LAN966x outband interrupt controller (OIC) maps the internal + interrupt sources of the LAN966x device to an external interrupt. + When the LAN966x device is used as a PCI device, the external interrupt is + routed to the PCI interrupt. + +properties: + compatible: + const: microchip,lan966x-oic + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - '#interrupt-cells' + - interrupt-controller + - interrupts + - reg + +additionalProperties: false + +examples: + - | + interrupt-controller@e00c0120 { + compatible = "microchip,lan966x-oic"; + reg = <0xe00c0120 0x190>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = <0>; + interrupt-parent = <&intc>; + }; +...