From patchwork Wed Jun 12 06:58:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pierre-Louis Bossart X-Patchwork-Id: 13694486 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 685DC13CFB0 for ; Wed, 12 Jun 2024 06:59:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718175568; cv=none; b=sS54P8ZVZPMWm+Cu1ex7CsRahPmPr1RepqqH3s/aYwa1nzHRdwytT81tPJPN9krWjeU4Gm8ytkHrLHRcszr5HpMtPxBOM2eAgsO7sLgEUujgBe7RAQYFBYUW7+1gx1wYx/Q7rlIhJpBQKGmYw6X/60Z6BNNqOfMZ1kEiBZoa9Q8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718175568; c=relaxed/simple; bh=crewVMHSfJKgeI4smrQVHU61rtSFJP+uy4uxd/EJzag=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GSrFxpKLZ93iBKQ10rmm6rAegP0x45R1uL2qn8BOR4BpbbgkEpmWuQ8QD4RrZrBtPELp7iHUMfYNFXLtn4AJw5IHYQqAjfZp1ca9c9tzktAIUXa9cq+FU+azyN0CiNydvRNorP49oArlrTVLbXOALDtWH9DZufd+bJ7g4eb1sQA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=myVRaExB; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="myVRaExB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718175567; x=1749711567; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=crewVMHSfJKgeI4smrQVHU61rtSFJP+uy4uxd/EJzag=; b=myVRaExB7ntcbJ2p9w00rsKzXBnHrlN+KVgP565FZrqW7uWqbS36HD42 IUsSHEqEatdXsg7jDj4S21d+QqCbhfhCG95Fp02JYxPNkxDKYExv/7Zn6 C0ewdllU0f8VKjQNiUkBOgdllKgxmhvjjF9qIHQW5+ifwjqz0quQSyBe0 UBPNdQZAE2Q7wLhtEWrBuyEeYCasTjnaZFbxhzLXW7aW5oH7S6MAhwMWu ie+5RpPeDRknjU4c27XLAGBs4zXw0J+7Tvs6OkS0F609ofAX6jVXO5AKo 3fJm2TWfpWFLuSptqkuqDsGu6a8IW2UzcN3H9qtr1Gy9k4MgqFX5kgMNY g==; X-CSE-ConnectionGUID: 6dYIC3jkQzqCefz02WSv/Q== X-CSE-MsgGUID: iB4rwsoKRKOMp/3MCN2VCw== X-IronPort-AV: E=McAfee;i="6600,9927,11100"; a="15147423" X-IronPort-AV: E=Sophos;i="6.08,232,1712646000"; d="scan'208";a="15147423" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 23:59:27 -0700 X-CSE-ConnectionGUID: /tB3R0R4SZ2p05eNkahrNA== X-CSE-MsgGUID: iExHUtZWQaawL98siFUsHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,232,1712646000"; d="scan'208";a="70486853" Received: from iklimasz-mobl1.ger.corp.intel.com (HELO pbossart-mobl6.intel.com) ([10.245.246.56]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 23:59:24 -0700 From: Pierre-Louis Bossart To: alsa-devel@alsa-project.org Cc: tiwai@suse.de, broonie@kernel.org, Bjorn Helgaas , linux-pci@vger.kernel.org, Fred Oh , Ranjani Sridharan , Bard Liao , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Pierre-Louis Bossart Subject: [PATCH 1/5] ASoC: SOF: Intel: add PTL specific power control register Date: Wed, 12 Jun 2024 08:58:54 +0200 Message-ID: <20240612065858.53041-2-pierre-louis.bossart@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240612065858.53041-1-pierre-louis.bossart@linux.intel.com> References: <20240612065858.53041-1-pierre-louis.bossart@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Fred Oh PTL has some differences from MTL/LNL. Need to use different register to power up. Reviewed-by: Ranjani Sridharan Reviewed-by: Bard Liao Reviewed-by: Péter Ujfalusi Signed-off-by: Fred Oh Signed-off-by: Pierre-Louis Bossart --- sound/soc/sof/intel/mtl.c | 16 ++++++++++++++-- sound/soc/sof/intel/mtl.h | 2 ++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index 1bf274509ee6..2b9d22ccf345 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -245,6 +245,18 @@ int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev) u32 cpa; u32 pgs; int ret; + u32 dsppwrctl; + u32 dsppwrsts; + const struct sof_intel_dsp_desc *chip; + + chip = get_chip_info(sdev->pdata); + if (chip->hw_ip_version > SOF_INTEL_ACE_2_0) { + dsppwrctl = PTL_HFPWRCTL2; + dsppwrsts = PTL_HFPWRSTS2; + } else { + dsppwrctl = MTL_HFPWRCTL; + dsppwrsts = MTL_HFPWRSTS; + } /* Set the DSP subsystem power on */ snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS, @@ -264,14 +276,14 @@ int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev) } /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */ - snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, + snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, dsppwrctl, MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG); usleep_range(1000, 1010); /* poll with timeout to check if operation successful */ pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK; - ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts, + ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, dsppwrsts, dsphfpwrsts, (dsphfpwrsts & pgs) == pgs, HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US); diff --git a/sound/soc/sof/intel/mtl.h b/sound/soc/sof/intel/mtl.h index 7acaa7e724f4..9ab4b21c960e 100644 --- a/sound/soc/sof/intel/mtl.h +++ b/sound/soc/sof/intel/mtl.h @@ -12,9 +12,11 @@ #define MTL_HFDSSCS_CPA_MASK BIT(24) #define MTL_HFSNDWIE 0x114C #define MTL_HFPWRCTL 0x1D18 +#define PTL_HFPWRCTL2 0x1D20 #define MTL_HfPWRCTL_WPIOXPG(x) BIT((x) + 8) #define MTL_HFPWRCTL_WPDSPHPXPG BIT(0) #define MTL_HFPWRSTS 0x1D1C +#define PTL_HFPWRSTS2 0x1D24 #define MTL_HFPWRSTS_DSPHPXPGS_MASK BIT(0) #define MTL_HFINTIPPTR 0x1108 #define MTL_IRQ_INTEN_L_HOST_IPC_MASK BIT(0)