From patchwork Fri Jun 28 11:59:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13716009 X-Patchwork-Delegate: kw@linux.com Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2669D155A23; Fri, 28 Jun 2024 12:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576003; cv=none; b=IsJHTVv0n9cyYjwA1chRHr4DxPQGrQRvK089/N2dp7qR6IsieXdtlV5ibsqAFOspgAGKC4S4Mufr1kOUnS4jR5ShdVgrOntofurbacRM1Ksu80m8YFGh3JB5/aizY3aIScm8Gm0iyGFld4ZefE0wvas9gGuBqHo5+MadXy3HESY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576003; c=relaxed/simple; bh=pnR4pmsg5MGAcoqhuGjuhjHJEgVUH86UycujeWipnZw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mOFT+zRL/aXujHgS8PeVYr3JAWBQyWJAIbYWCdjhxl/yQWsLJbMhJPf4sMWvJVY4tZWLvGR9LLVbSTonkvaFsgIvXXE7AaG9XQt2pjGwof9KzsQ2Beu/dLHX6aptcfT1t80yCxgk+PjO/Sg4HiuU5yAlxtIz0Lv/ydM53ZsXsyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=AugpjjNI; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="AugpjjNI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1719576001; x=1751112001; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pnR4pmsg5MGAcoqhuGjuhjHJEgVUH86UycujeWipnZw=; b=AugpjjNIx6BmdjkizUQQCrRd+GpNzzQxGMYakfaOCxIQv6qC45dMg6bZ IaYGw7K2DeZg+N5APYRtBD3G6Q4AYd/wZ58f5HmT5glNqg6NI65WbuHgB XxnOSyVoGnOb/tt14myyVV1KB6Xf3HFkXUFprayJH/tyfbYOXmzqcBaVJ erUN7bRUzlRBGaGO8+ycZAmQn1dcb1+ZMBJQdItcUdp9rioPorYCfQ6ZA OzTfudxkQdTH1dRz02IQ5/2XEt18BIOiRN1wik5ItW0QlzQOuN6H2iqPf C6NWHNJNZFL2H2VP3VzFbss9gBOsyuOa/x29i+WpU8+EkZ92A2GfvTxDS A==; X-CSE-ConnectionGUID: fhzcQ281QiKf1QfzQI0hzg== X-CSE-MsgGUID: 7a9N9JiwQoaqIAb8otbLqA== X-IronPort-AV: E=Sophos;i="6.09,169,1716274800"; d="scan'208";a="259502560" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Jun 2024 05:00:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 28 Jun 2024 04:59:27 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 28 Jun 2024 04:59:25 -0700 From: To: , CC: , , , , , , , , , , Subject: [PATCH v6 1/3] PCI: microchip: Fix outbound address translation tables Date: Fri, 28 Jun 2024 12:59:21 +0100 Message-ID: <20240628115923.4133286-2-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628115923.4133286-1-daire.mcnamara@microchip.com> References: <20240628115923.4133286-1-daire.mcnamara@microchip.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daire McNamara On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of three general-purpose Fabric Interface Controller (FIC) buses that encapsulate an AXI-M interface. That FIC is responsible for managing the translations of the upper 32-bits of the AXI-M address. On MPFS, the Root Port driver needs to take account of that outbound address translation done by the parent FIC bus before setting up its own outbound address translation tables. In all cases on MPFS, the remaining outbound address translation tables are 32-bit only. Limit the outbound address translation tables to 32-bit only. This necessitates changing a size_t in mc_pcie_setup_window to a resource_size_t to avoid a compile error on 32-bit platforms. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") Signed-off-by: Daire McNamara Acked-by: Conor Dooley --- drivers/pci/controller/pcie-microchip-host.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 137fb8570ba2..47c397ae515a 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -23,6 +23,8 @@ /* Number of MSI IRQs */ #define MC_MAX_NUM_MSI_IRQS 32 +#define MC_OUTBOUND_TRANS_TBL_MASK GENMASK(31, 0) + /* PCIe Bridge Phy and Controller Phy offsets */ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u #define MC_PCIE1_CTRL_ADDR 0x0000a000u @@ -933,7 +935,7 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port) static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size) + resource_size_t size) { u32 atr_sz = ilog2(size) - 1; u32 val; @@ -983,7 +985,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, if (resource_type(entry->res) == IORESOURCE_MEM) { pci_addr = entry->res->start - entry->offset; mc_pcie_setup_window(bridge_base_addr, index, - entry->res->start, pci_addr, + entry->res->start & MC_OUTBOUND_TRANS_TBL_MASK, + pci_addr, resource_size(entry->res)); index++; } @@ -1117,9 +1120,8 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & MC_OUTBOUND_TRANS_TBL_MASK, + 0, resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win);