From patchwork Fri Jun 28 11:59:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13716011 X-Patchwork-Delegate: kw@linux.com Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2060E1586E7; Fri, 28 Jun 2024 12:00:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576004; cv=none; b=Iyb5m60yA8nsSaNJ4/E2Lq8rw4aZfbj5gek1+rrCc8XX+AQBHbv1KKafmrr480WiIe7wMV0QaavpQZ63MPQl6eqgPQ4Oy+6D3IbyA4NfiPH7K66qG3YR0URtx0AGSwSJ9kPOhMeud7iLzYCdOBCzndWlinzN9FufGBK3UO1UHDc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719576004; c=relaxed/simple; bh=jiUij3wRRe5sE48zPdwi6+NvzYyJIr+GpOYj/SVthjg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lSKL6VFDwKEkpSwFLtmluJ8fzD8xnqffVOG/iiYPV02mPs6cChZ2FQdRo5Bjgnvr+awTcdGo1BS3xrn7FcoauqUA04CFh7NeueGjybKY9kALWxt0cgMjZUYtKbm6sY+CuXkv7io3MPrnYdEnCUrBumiXdM2F0fLKHzwEGvLuzjw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=D+I1oyoI; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="D+I1oyoI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1719576003; x=1751112003; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jiUij3wRRe5sE48zPdwi6+NvzYyJIr+GpOYj/SVthjg=; b=D+I1oyoIQEKNgKxFe7uF9q/0ip9TdFQNTlEninAQfeudr+c6s0B2LxmN sWcnvAv+SDOOFe0Uh2EvL8BESHNrE9whO9y6Xd0cSpytURZnFv/sPO/J4 1fCd9ypNMoYm6l34MZjMcPRm1WpjgTuavf0I3sQfhom8PujdeWsf1/dXG S3lLxCl8HkN2gFhM6lm1IQv0VK5CbPJly+n6FPrkwF8x1g6DuxOn7WSjN HNP5qDjcEQEYqmdPHZ+v3GF5d/ZK9Od7mTa442nVI9pTS0f/m/eH3PzoX VBR3zzv+lgVQureo+fQBzbn1hyCePAGrMnMCxh53FkBH7QCGtXTt1SreZ A==; X-CSE-ConnectionGUID: fhzcQ281QiKf1QfzQI0hzg== X-CSE-MsgGUID: R+AVEiQ/TTmD0N108NexvA== X-IronPort-AV: E=Sophos;i="6.09,169,1716274800"; d="scan'208";a="259502562" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Jun 2024 05:00:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 28 Jun 2024 04:59:34 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 28 Jun 2024 04:59:30 -0700 From: To: , CC: , , , , , , , , , , Subject: [PATCH v6 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent Date: Fri, 28 Jun 2024 12:59:23 +0100 Message-ID: <20240628115923.4133286-4-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628115923.4133286-1-daire.mcnamara@microchip.com> References: <20240628115923.4133286-1-daire.mcnamara@microchip.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Conor Dooley PolarFire SoC may be configured in a way that requires non-coherent DMA handling. On RISC-V, buses are coherent by default & the dma-noncoherent property is required to denote buses or devices that are non-coherent. Signed-off-by: Conor Dooley Signed-off-by: Daire McNamara Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index f7a3c2636355..c84e1ae20532 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -52,6 +52,8 @@ properties: items: pattern: '^fic[0-3]$' + dma-noncoherent: true + interrupts: minItems: 1 items: