From patchwork Mon Jul 29 14:22:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13745012 Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F36F716B74C for ; Mon, 29 Jul 2024 14:23:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722263039; cv=none; b=EISpA1eXYXdZOtH5Z2A+ijSVlO7VnXPUseEpB2zjpbKsg6O2L6JZxa0pWkpUUuVkWzB/4p/0jO9iA1zOY7tNGLedDFlkK4KAa3dvOS4WLN3peqJjjVJzuCi+5P7ssstm68shmeDs1v0FbRJFY1QKyk7PwpqHIPOWGeZfv3pS0ds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722263039; c=relaxed/simple; bh=mxjx/BlUYG2w0mz5G76SIHP2sKV9B9/KnJhQw3W83Pk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YhBVMugCfUq5c+YSdlNLkMx9k4oPyCaFOUa5w6sGv8utIsxgnlH64Xjbg0avybLE1RI8n1+r14XaFn0koyVAo0KXuZklsEiDBP3iuXTwE7fjcCFdwlKsz2FL+Sv1TCtV3XNp1uE1grIcD6dCDdKw3VQO2VRPwe30KVMdvpZclCU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=GmBTR4qW; arc=none smtp.client-ip=209.85.215.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="GmBTR4qW" Received: by mail-pg1-f177.google.com with SMTP id 41be03b00d2f7-7a1be7b7bb5so2441201a12.0 for ; Mon, 29 Jul 2024 07:23:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1722263037; x=1722867837; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=faQAT1JYz4uKgs1JiW6v4seMVdvUx1pSLIJRc+OrnCU=; b=GmBTR4qWenfCPpZmI+zLN16mBY3XsezXgJKkUTA1CuJ8l76cxs4ywzHAftsfMODZML WQlbmBv6oN0QxbcoxXG7BvP6N7h+Lt6doYiAqctJQEwA7HvZnidgH7q3ZlEopADEi/yI nT8ieOCxIIGBSqU0cHwekoy7sZvr8LgL4v42CZyOR+u7YlOsrdACl2aiDg6rGvjhrcDl zRr314KAY1feT1x1h4FtG+40gS5IAjVGTxK1z3as+71ggliIlkuLYH/dhIROrURkaNX3 l5MGIDG4/J4n9Tdc3RiZmLWiSw1F9p6SMCkztsYyJE/1/ChL/pWzESB7gTeHJbBjfU6L rMhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722263037; x=1722867837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=faQAT1JYz4uKgs1JiW6v4seMVdvUx1pSLIJRc+OrnCU=; b=n55rEjs9L9LP06LPeXQskIxXsBHzWSGSs8hSbKqOw/TLhYFM6UxQfVj/zT46BVH1QM e0GbwaWdsOnvaDbiL8GFOOGqPB0oBIE08EDZoZz1hoHhy/U/bsfrmS9Wknx0tqDYRsj4 /0sZDGdV28svu1UqKfIWX2B3e82ubnb/59ABBaKnj40N9buXQ1RtWRzrumuKnVnftMoZ EJD/vFlEEqjruXjsBC6/fauQAUBSUNYrhtZOnjcPCAZ3V1SFdTVyWvs8NWP0f4WoZcMf eWJDgO8eZnRpFzxDkkmzAex3dg0Y/bDfNS0Uw0ea2vGin35ZLBbyMiQAaSp+rn0Rgxtm WC4w== X-Forwarded-Encrypted: i=1; AJvYcCX66OfIp31XT7vyrtuaU13H9EwWq51Ak4AIJS0Z0DUyDoAYmksPq24A09USdLMKEHShrQy1+8SkQV/cMAPfNa061zScBAITQSRs X-Gm-Message-State: AOJu0YwDS5ElcemXlFLOg0nlBuJnCBRRB9wqSwqaCtNTEzb6sEMMGddt 5YYDXSZAsGrUx5DNsnNf4t2NC4TdJ+KdDWbXGGgPeZSFl0eXnzSdAF1vVpiMpx0= X-Google-Smtp-Source: AGHT+IHlNJOaWOv9P6EA+WSzfVqrKSPrT5Gc2L8g3dIqAtwsXWtcNKuiNkZFmX1M/bo3S6ce4Gfr2g== X-Received: by 2002:a05:6a20:4394:b0:1be:e6d8:756e with SMTP id adf61e73a8af0-1c4a1512bf4mr10901917637.53.1722263037394; Mon, 29 Jul 2024 07:23:57 -0700 (PDT) Received: from sunil-pc.tail07344b.ts.net ([106.51.198.16]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fed7fa988dsm83512965ad.263.2024.07.29.07.23.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jul 2024 07:23:56 -0700 (PDT) From: Sunil V L To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Haibo Xu , Atish Kumar Patra , Drew Fustini , Sunil V L Subject: [PATCH v7 11/17] ACPI: RISC-V: Initialize GSI mapping structures Date: Mon, 29 Jul 2024 19:52:33 +0530 Message-ID: <20240729142241.733357-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240729142241.733357-1-sunilvl@ventanamicro.com> References: <20240729142241.733357-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 RISC-V has PLIC and APLIC in MADT as well as namespace devices. Initialize the list of those structures using MADT and namespace devices to create mapping between the ACPI handle and the GSI ranges. This will be used later to add dependencies. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 22 ++++++ drivers/acpi/riscv/init.c | 2 + drivers/acpi/riscv/init.h | 4 + drivers/acpi/riscv/irq.c | 147 +++++++++++++++++++++++++++++++++++ 4 files changed, 175 insertions(+) create mode 100644 drivers/acpi/riscv/init.h diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 8e10a94430a2..44a0b128c602 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -16,4 +16,26 @@ void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); struct fwnode_handle *riscv_get_intc_hwnode(void); +#ifdef CONFIG_ACPI + +enum riscv_irqchip_type { + ACPI_RISCV_IRQCHIP_INTC = 0x00, + ACPI_RISCV_IRQCHIP_IMSIC = 0x01, + ACPI_RISCV_IRQCHIP_PLIC = 0x02, + ACPI_RISCV_IRQCHIP_APLIC = 0x03, +}; + +int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, + u32 *id, u32 *nr_irqs, u32 *nr_idcs); +struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi); + +#else +static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, + u32 *id, u32 *nr_irqs, u32 *nr_idcs) +{ + return 0; +} + +#endif /* CONFIG_ACPI */ + #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index 5f7571143245..22db97f7a772 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -6,7 +6,9 @@ */ #include +#include "init.h" void __init acpi_riscv_init(void) { + riscv_acpi_init_gsi_mapping(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h new file mode 100644 index 000000000000..0b9a07e4031f --- /dev/null +++ b/drivers/acpi/riscv/init.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +void __init riscv_acpi_init_gsi_mapping(void); diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index 835eb6eccd53..9028787c73a7 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -6,6 +6,21 @@ #include #include +#include + +#include "init.h" + +struct riscv_ext_intc_list { + acpi_handle handle; + u32 gsi_base; + u32 nr_irqs; + u32 nr_idcs; + u32 id; + u32 type; + struct list_head list; +}; + +LIST_HEAD(ext_intc_list); static int irqchip_cmp_func(const void *in0, const void *in1) { @@ -31,3 +46,135 @@ void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr) return; sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL); } + +static acpi_status riscv_acpi_update_gsi_handle(u32 gsi_base, acpi_handle handle) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct list_head *i, *tmp; + + list_for_each_safe(i, tmp, &ext_intc_list) { + ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list); + if (gsi_base == ext_intc_element->gsi_base) { + ext_intc_element->handle = handle; + return AE_OK; + } + } + + return AE_NOT_FOUND; +} + +int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, + u32 *id, u32 *nr_irqs, u32 *nr_idcs) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct list_head *i; + + list_for_each(i, &ext_intc_list) { + ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list); + if (ext_intc_element->handle == ACPI_HANDLE_FWNODE(fwnode)) { + *gsi_base = ext_intc_element->gsi_base; + *id = ext_intc_element->id; + *nr_irqs = ext_intc_element->nr_irqs; + if (nr_idcs) + *nr_idcs = ext_intc_element->nr_idcs; + + return 0; + } + } + + return -ENODEV; +} + +struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct acpi_device *adev; + struct list_head *i; + + list_for_each(i, &ext_intc_list) { + ext_intc_element = list_entry(i, struct riscv_ext_intc_list, list); + if (gsi >= ext_intc_element->gsi_base && + gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs)) { + adev = acpi_fetch_acpi_dev(ext_intc_element->handle); + if (!adev) + return NULL; + + return acpi_fwnode_handle(adev); + } + } + + return NULL; +} + +static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, u32 nr_idcs, + u32 id, u32 type) +{ + struct riscv_ext_intc_list *ext_intc_element; + + ext_intc_element = kzalloc(sizeof(*ext_intc_element), GFP_KERNEL); + if (!ext_intc_element) + return -ENOMEM; + + ext_intc_element->gsi_base = gsi_base; + ext_intc_element->nr_irqs = nr_irqs; + ext_intc_element->nr_idcs = nr_idcs; + ext_intc_element->id = id; + list_add_tail(&ext_intc_element->list, &ext_intc_list); + return 0; +} + +static acpi_status __init riscv_acpi_create_gsi_map(acpi_handle handle, u32 level, + void *context, void **return_value) +{ + acpi_status status; + u64 gbase; + + if (!acpi_has_method(handle, "_GSB")) { + acpi_handle_err(handle, "_GSB method not found\n"); + return AE_ERROR; + } + + status = acpi_evaluate_integer(handle, "_GSB", NULL, &gbase); + if (ACPI_FAILURE(status)) { + acpi_handle_err(handle, "failed to evaluate _GSB method\n"); + return status; + } + + status = riscv_acpi_update_gsi_handle((u32)gbase, handle); + if (ACPI_FAILURE(status)) { + acpi_handle_err(handle, "failed to find the GSI mapping entry\n"); + return status; + } + + return AE_OK; +} + +static int __init riscv_acpi_aplic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_aplic *aplic = (struct acpi_madt_aplic *)header; + + return riscv_acpi_register_ext_intc(aplic->gsi_base, aplic->num_sources, aplic->num_idcs, + aplic->id, ACPI_RISCV_IRQCHIP_APLIC); +} + +static int __init riscv_acpi_plic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_plic *plic = (struct acpi_madt_plic *)header; + + return riscv_acpi_register_ext_intc(plic->gsi_base, plic->num_irqs, 0, + plic->id, ACPI_RISCV_IRQCHIP_PLIC); +} + +void __init riscv_acpi_init_gsi_mapping(void) +{ + /* There can be either PLIC or APLIC */ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, riscv_acpi_plic_parse_madt, 0) > 0) { + acpi_get_devices("RSCV0001", riscv_acpi_create_gsi_map, NULL, NULL); + return; + } + + if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_madt, 0) > 0) + acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL); +}