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Tue, 30 Jul 2024 06:42:45 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , John Stultz , Thomas Gleixner , "Anna-Maria Behnsen" , Frederic Weisbecker , , Bjorn Helgaas , , Ingo Molnar , Borislav Petkov , Dave Hansen , , Carolina Jubran , Bar Shapira , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net-next V3 1/3] net/mlx5: Add support for MTPTM and MTCTR registers Date: Tue, 30 Jul 2024 16:40:52 +0300 Message-ID: <20240730134055.1835261-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730134055.1835261-1-tariqt@nvidia.com> References: <20240730134055.1835261-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A1:EE_|SJ2PR12MB8133:EE_ X-MS-Office365-Filtering-Correlation-Id: c200e9ab-ed22-4540-0435-08dcb09d8c19 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: /PzYTmE4nebYJJ8BRezdYHcdUs0wudZK1A2vZErZOUA/9inNF0Yehf4FJ8chn/zNHnerT/BhQ6ffSZubnc6Fup4TowIoaNM7oJn1yMeOt/2926swWZK5VzsKSBZgf94dAIhmUl3+4rmsv8imfo1d8/fDpZ/1YWCfjqN4/T4006aTAcc5U9sLP9fJXFOvqbIFsAa8TC482vtW4pLdGLEZIG3yLtfZCZkb9A/QBcspq1cVyhaTpl/RN8nJFDmh+TMlB7odj3L1Cd64xKmRp7lt8UXy21TnrMNinp7gbwpdM6xCgmaRM5RFL48vZVOsSSxeIjgQG+Yk4GmS6cY9r9XR88rbwqpxIZcta09CZX6RmMJr69+M2qRFA0e/f6Ix2/U9lXrgEAXOl9qJVBI/V4PzdvovmB0bLCmDGBkfSWYzODDJpDnRoliV60LlfPKaydzgR73xlq9C1n3T5kse+hN1PQtyERB4BGHESYqqITLE4yrnAkC7Luf/wObPIZe/XxI1dhk5ILOfnYtBOWonHMxg3fvEaXUVOQSOs7z/NbCAylCbkSOIrdj8nU+Ki6xjg3a3Og8sNeJHmIvRtCNhVV7vl9fUeV2m5vhhvtnafrjIRW9UhA1XYyzbYzqUvjLbtnf4nfo8iv1zuJdXIu2x3s6gU6EJa/MW+MbxzkMZ3FsonRNb1z+M74aCBK0Yq9snENdeIRP87cy4LhSzPrEEeCg2cHIxpIkHObGNnzyAaclp1s07V3zKkjJ1pR4oQBZ2Z095adguvej/jZRHs6q7bUueZ7GwToCJHU8Ub1QEM3kn8QQNqsjse6WzdX8bTgd8fxDxJ5SE2rIv/S5+ux8Ke/faX4ESAmp4JYO3CyRzDISG9R5Gt7/49CFR9MJSlxUvd6PNEvrxWfkMH1PYsCRMjYorvyaSZcgOqcA5d5iIWmzh05HQHTTXGT5Bn1U2FZIJRokjWEhjLvTbJ6WKV0u1H4MwpYXR927f8GY+icQcCjVsUngQofc5QZa9erKw2hZwZdLy4wMWMBBZ38lffwz1D9ffPNrPj1IDyLGcf9tXoYBPOg+rkos8Un+FMYRuzFfD/5qXBZ8rCcD7Y6s0+sU2jJmPJM2pngVIBeA7IpymkoSUEdFfia/oXhQPhNspt87YdLRh46mcBfTquhsvkYIXXZ3o9c+NHaeR3Rn6WGnQHZi55AqGd8DXH8/7eOLcjPrZUY3yJtiE9/IvsqfK9J4Z9fkfdJSckRamVbj/9bGv4IFGXCJmSznz7RXOaG7RwrPd8FO4GP9Q/BSLXRH0/qBHznB2dgaefYOG6i+MsjHKuAEqGYMNZG4DXf4uJ5Cyc8OMGa8wgK8jCx1I45s/EDhEsV6CAWPgNLfEzFgUvsPswh8Xy7Y96xWo+8PC3KH3mkv3d1bYgyOZ6Dx0W5Xd619nEnM+4/2ZpfPTiHuTbnlUOj39SLoaurQC8d1MIVjZRGyAJBlT X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 13:43:08.5321 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c200e9ab-ed22-4540-0435-08dcb09d8c19 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8133 From: Rahul Rameshbabu Make Management Precision Time Measurement (MTPTM) register and Management Cross Timestamp (MTCTR) register usable in mlx5 driver. Signed-off-by: Rahul Rameshbabu Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 1 + include/linux/mlx5/device.h | 7 +++- include/linux/mlx5/driver.h | 2 + include/linux/mlx5/mlx5_ifc.h | 43 ++++++++++++++++++++ 4 files changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c index b61b7d966114..76ad46bf477d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c @@ -224,6 +224,7 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) if (MLX5_CAP_GEN(dev, mcam_reg)) { mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128); mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F); + mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9180_0x91FF); } if (MLX5_CAP_GEN(dev, qcam_reg)) diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index ba875a619b97..a94bc9e3af96 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1243,7 +1243,8 @@ enum mlx5_pcam_feature_groups { enum mlx5_mcam_reg_groups { MLX5_MCAM_REGS_FIRST_128 = 0x0, MLX5_MCAM_REGS_0x9100_0x917F = 0x2, - MLX5_MCAM_REGS_NUM = 0x3, + MLX5_MCAM_REGS_0x9180_0x91FF = 0x3, + MLX5_MCAM_REGS_NUM = 0x4, }; enum mlx5_mcam_feature_groups { @@ -1392,6 +1393,10 @@ enum mlx5_qcam_feature_groups { MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ mng_access_reg_cap_mask.access_regs2.reg) +#define MLX5_CAP_MCAM_REG3(mdev, reg) \ + MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9180_0x91FF], \ + mng_access_reg_cap_mask.access_regs3.reg) + #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index a96438ded15f..9f42834f57c5 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -159,6 +159,8 @@ enum { MLX5_REG_MSECQ = 0x9155, MLX5_REG_MSEES = 0x9156, MLX5_REG_MIRC = 0x9162, + MLX5_REG_MTPTM = 0x9180, + MLX5_REG_MTCTR = 0x9181, MLX5_REG_SBCAM = 0xB01F, MLX5_REG_RESOURCE_DUMP = 0xC000, MLX5_REG_DTOR = 0xC00E, diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index cab228cf51c6..234ad6f16e92 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -10401,6 +10401,18 @@ struct mlx5_ifc_mcam_access_reg_bits2 { u8 regs_31_to_0[0x20]; }; +struct mlx5_ifc_mcam_access_reg_bits3 { + u8 regs_127_to_96[0x20]; + + u8 regs_95_to_64[0x20]; + + u8 regs_63_to_32[0x20]; + + u8 regs_31_to_2[0x1e]; + u8 mtctr[0x1]; + u8 mtptm[0x1]; +}; + struct mlx5_ifc_mcam_reg_bits { u8 reserved_at_0[0x8]; u8 feature_group[0x8]; @@ -10413,6 +10425,7 @@ struct mlx5_ifc_mcam_reg_bits { struct mlx5_ifc_mcam_access_reg_bits access_regs; struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; + struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; u8 reserved_at_0[0x80]; } mng_access_reg_cap_mask; @@ -11166,6 +11179,34 @@ struct mlx5_ifc_mtmp_reg_bits { u8 sensor_name_lo[0x20]; }; +struct mlx5_ifc_mtptm_reg_bits { + u8 reserved_at_0[0x10]; + u8 psta[0x1]; + u8 reserved_at_11[0xf]; + + u8 reserved_at_20[0x60]; +}; + +enum { + MLX5_MTCTR_REQUEST_NOP = 0x0, + MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, + MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, + MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, +}; + +struct mlx5_ifc_mtctr_reg_bits { + u8 first_clock_timestamp_request[0x8]; + u8 second_clock_timestamp_request[0x8]; + u8 reserved_at_10[0x10]; + + u8 first_clock_valid[0x1]; + u8 second_clock_valid[0x1]; + u8 reserved_at_22[0x1e]; + + u8 first_clock_timestamp[0x40]; + u8 second_clock_timestamp[0x40]; +}; + union mlx5_ifc_ports_control_registers_document_bits { struct mlx5_ifc_bufferx_reg_bits bufferx_reg; struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; @@ -11230,6 +11271,8 @@ union mlx5_ifc_ports_control_registers_document_bits { struct mlx5_ifc_mrtc_reg_bits mrtc_reg; struct mlx5_ifc_mtcap_reg_bits mtcap_reg; struct mlx5_ifc_mtmp_reg_bits mtmp_reg; + struct mlx5_ifc_mtptm_reg_bits mtptm_reg; + struct mlx5_ifc_mtctr_reg_bits mtctr_reg; u8 reserved_at_0[0x60e0]; };