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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF00020E66.mail.protection.outlook.com (10.167.249.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7849.8 via Frontend Transport; Wed, 7 Aug 2024 15:17:41 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 7 Aug 2024 10:17:40 -0500 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Wed, 7 Aug 2024 10:17:40 -0500 From: Stewart Hildebrand To: Bjorn Helgaas CC: Stewart Hildebrand , , Subject: [PATCH v3 2/8] PCI: Don't unnecessarily disable memory decoding Date: Wed, 7 Aug 2024 11:17:11 -0400 Message-ID: <20240807151723.613742-3-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240807151723.613742-1-stewart.hildebrand@amd.com> References: <20240807151723.613742-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E66:EE_|CYXPR12MB9317:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d1553af-f625-41fc-e303-08dcb6f4148e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 15:17:41.2326 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d1553af-f625-41fc-e303-08dcb6f4148e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9317 If alignment is requested for a device and all the BARs are already sufficiently aligned, there is no need to disable memory decoding for the device. Add a check for this scenario to save a PCI config space access. Also, there is no need to disable memory decoding if already disabled, since the bit in question (PCI_COMMAND_MEMORY) is a RW bit. Make the write conditional to save a PCI config space access. Signed-off-by: Stewart Hildebrand --- v2->v3: * no change v1->v2: * new subject (was: "PCI: don't clear already cleared bit") * don't disable memory decoding if alignment is not needed --- drivers/pci/pci.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e3a49f66982d..acecdd6edd5a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6564,7 +6564,7 @@ static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, return align; } -static void pci_request_resource_alignment(struct pci_dev *dev, int bar, +static bool pci_request_resource_alignment(struct pci_dev *dev, int bar, resource_size_t align, bool resize) { struct resource *r = &dev->resource[bar]; @@ -6572,17 +6572,17 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar, resource_size_t size; if (!(r->flags & IORESOURCE_MEM)) - return; + return false; if (r->flags & IORESOURCE_PCI_FIXED) { pci_info(dev, "%s %pR: ignoring requested alignment %#llx\n", r_name, r, (unsigned long long)align); - return; + return false; } size = resource_size(r); if (size >= align) - return; + return false; /* * Increase the alignment of the resource. There are two ways we @@ -6625,6 +6625,8 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar, r->end = r->start + size - 1; } r->flags |= IORESOURCE_UNSET; + + return true; } /* @@ -6640,7 +6642,7 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) struct resource *r; resource_size_t align; u16 command; - bool resize = false; + bool resize = false, align_needed = false; /* * VF BARs are read-only zero according to SR-IOV spec r1.1, sec @@ -6662,12 +6664,21 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) return; } - pci_read_config_word(dev, PCI_COMMAND, &command); - command &= ~PCI_COMMAND_MEMORY; - pci_write_config_word(dev, PCI_COMMAND, command); + for (i = 0; i <= PCI_ROM_RESOURCE; i++) { + bool ret; - for (i = 0; i <= PCI_ROM_RESOURCE; i++) - pci_request_resource_alignment(dev, i, align, resize); + ret = pci_request_resource_alignment(dev, i, align, resize); + align_needed = align_needed || ret; + } + + if (!align_needed) + return; + + pci_read_config_word(dev, PCI_COMMAND, &command); + if (command & PCI_COMMAND_MEMORY) { + command &= ~PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, command); + } /* * Need to disable bridge's resource window,