From patchwork Fri Sep 13 14:36:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13803559 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74C9A1BC2A; Fri, 13 Sep 2024 14:37:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726238237; cv=none; b=JUKHwe2TzIvkZcgChwOPjde4M9sOaCVeNS0fbtBzByI1crsfxzBucT+zm//RO9If9QpU/YZY+tnWieKYD8T+lUWfGW0m44N3qN+YTJ7cg14lzjPGG/QoW55NJKIjjxwhnigK8IXqRHkNxwljUUf5S4tyqXTTccw0MADluRyvZFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726238237; c=relaxed/simple; bh=evQuuqWFYfqXRdK4cCd1u1trTMAUjrTXVQa7VhzPyW4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=ePkRVc5eQ4jtJQI30LI6XmKM2fuJVILO403PlaRRziQS5aiGsflRwpQSyzVHwrh8B1P4IbKr2Wr7G5tOUriT+4jUUPCOunPJNVF8Lt21mrHzjwyTZe+csjlkZblr10IA/PjcNPtXRvmlc2gTbqab/iHhRa1tny0lg27SyTiPRRY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gRTI9DiI; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gRTI9DiI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726238235; x=1757774235; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=evQuuqWFYfqXRdK4cCd1u1trTMAUjrTXVQa7VhzPyW4=; b=gRTI9DiIoEOwST/sUYJYmBL5fIevTRhX20FjRw0Yd9mSlByr56A3+P5f k7kQuB8kdnFSVIw4a5Od3GqJ2hBGGEG3jyS30WKeAmA7wqq44wOYqY7c4 KNW39D2oL41YgVEoVKV+wxm0DyBU4CEipjq+kQHPaiVIF4Cm2FAOGLhWo sptEpiS4DYAq31/rWA4a3Jp5VGjzv1iCO7T1nTUmqVQjIOyOaPhY069Xx tzyomxMAtx1km1RFkPbPWna5ZDyMCx1FuK2WmqIpjk65Ts9Yx9jevIsN8 nQxRs2iAXt9t1n0YJKkc/DCgpXzWM//7O4hI+uAYDPJZdDFl7KytAJVlj w==; X-CSE-ConnectionGUID: 0I1DsqhZQi+r4MoqCCSdDQ== X-CSE-MsgGUID: GH6yxMhaTfm6pNxvhdIKJA== X-IronPort-AV: E=McAfee;i="6700,10204,11194"; a="25075268" X-IronPort-AV: E=Sophos;i="6.10,226,1719903600"; d="scan'208";a="25075268" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2024 07:36:55 -0700 X-CSE-ConnectionGUID: 0fVSlgULT3C5aQJHTibMUw== X-CSE-MsgGUID: Z9rDjUDFTtWBzE4BBhW08Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,226,1719903600"; d="scan'208";a="67934647" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.154]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2024 07:36:52 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Mahesh J Salgaonkar , Oliver O'Halloran , Lukas Wunner , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-kernel@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v6 1/8] PCI: Don't expose pcie_read_tlp_log() outside of PCI subsystem Date: Fri, 13 Sep 2024 17:36:25 +0300 Message-Id: <20240913143632.5277-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240913143632.5277-1-ilpo.jarvinen@linux.intel.com> References: <20240913143632.5277-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 pcie_read_tlp_log() was exposed by the commit 0a5a46a6a61b ("PCI/AER: Generalize TLP Header Log reading") but this is now considered a mistake. No drivers outside of PCI subsystem should build their own diagnostic logging but should rely on PCI core doing it for them. There's currently one driver (ixgbe) doing it independently which was the initial reason why the export was added but it was decided by the PCI maintainer that it's something that should be eliminated. Remove the unwanted EXPORT of pcie_read_tlp_log() and remove it from include/linux/aer.h. Link: https://lore.kernel.org/all/20240322193011.GA701027@bhelgaas/ Signed-off-by: Ilpo Järvinen --- drivers/pci/pci.c | 1 - drivers/pci/pci.h | 4 ++++ include/linux/aer.h | 2 -- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e3a49f66982d..378fc645424f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1121,7 +1121,6 @@ int pcie_read_tlp_log(struct pci_dev *dev, int where, return 0; } -EXPORT_SYMBOL_GPL(pcie_read_tlp_log); /** * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 79c8398f3938..b4fc6726eab3 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -4,6 +4,8 @@ #include +struct pcie_tlp_log; + /* Number of possible devfns: 0.0 to 1f.7 inclusive */ #define MAX_NR_DEVFNS 256 @@ -482,6 +484,8 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); #endif /* CONFIG_PCIEAER */ +int pcie_read_tlp_log(struct pci_dev *dev, int where, struct pcie_tlp_log *log); + #ifdef CONFIG_PCIEPORTBUS /* Cached RCEC Endpoint Association */ struct rcec_ea { diff --git a/include/linux/aer.h b/include/linux/aer.h index 4b97f38f3fcf..190a0a2061cd 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -37,8 +37,6 @@ struct aer_capability_regs { u16 uncor_err_source; }; -int pcie_read_tlp_log(struct pci_dev *dev, int where, struct pcie_tlp_log *log); - #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev);