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Thu, 19 Sep 2024 22:04:05 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%4]) with mapi id 15.20.7982.018; Thu, 19 Sep 2024 22:04:05 +0000 From: Frank Li Date: Thu, 19 Sep 2024 18:03:05 -0400 Subject: [PATCH 5/9] PCI: dwc: ep: Replace phys_base and addr_size with range Message-Id: <20240919-pcie_ep_range-v1-5-b3e9d62780b7@nxp.com> References: <20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com> In-Reply-To: <20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Abraham I , Saravana Kannan , Jingoo Han , Gustavo Pimentel , Jesper Nilsson , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, =?utf-8?q?Krzys?= =?utf-8?q?ztof_Wilczy=C5=84ski?= , Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; 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But in some systems such as i.MX8QXP, they are different. Previously, we used the cpu_addr_fixup() hook function to handle address translation. However, the device tree can use the common 'ranges' property to indicate how CPU and PCI addresses are translated. Replace the fields 'phys_base' and 'addr_size' in struct dw_pcie_ep with struct of_pci_range 'range'. The of_pci_range already includes cpu_addr and size information. Prepare to add 'ranges' support. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-artpec6.c | 2 +- drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++--- drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index f8e7283dacd47..f93d3c7a980c8 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -104,7 +104,7 @@ static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr) case DW_PCIE_RC_TYPE: return cpu_addr - pp->cfg0_base; case DW_PCIE_EP_TYPE: - return cpu_addr - ep->phys_base; + return cpu_addr - ep->range.cpu_addr; default: dev_err(pci->dev, "UNKNOWN device type\n"); } diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 43ba5c6738df1..feac1a435f764 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -872,8 +872,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (!res) return -EINVAL; - ep->phys_base = res->start; - ep->addr_size = resource_size(res); + ep->range.cpu_addr = ep->range.pci_addr = res->start; + ep->range.size = resource_size(res); if (ep->ops->pre_init) ep->ops->pre_init(ep); @@ -891,7 +891,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ret < 0) epc->max_functions = 1; - ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, + ret = pci_epc_mem_init(epc, ep->range.cpu_addr, ep->range.size, ep->page_size); if (ret < 0) { dev_err(dev, "Failed to initialize address space\n"); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35aa..59109a32b2afc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -409,8 +410,7 @@ struct dw_pcie_ep { struct pci_epc *epc; struct list_head func_list; const struct dw_pcie_ep_ops *ops; - phys_addr_t phys_base; - size_t addr_size; + struct of_pci_range range; size_t page_size; u8 bar_to_atu[PCI_STD_NUM_BARS]; phys_addr_t *outbound_addr;