From patchwork Thu Oct 17 01:58:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13839291 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65E4233997; Thu, 17 Oct 2024 01:59:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729130352; cv=none; b=kDqOz6HhSi8JpFucQHe6ggwm2hMwqYJIFpD3GfOCdkd75qWuhQCwvwuPN8zuqJJxul+9Jq8Oryz4/A5H9WWUBJI8v2iWf6+BwlQM76/KrUMyICSkaXRYBS3H/Ver8OgSMQwN78MCG+YkUCe5NW8UuQPJyZRc9iIjpG9oVWgPPLQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729130352; c=relaxed/simple; bh=tNqaONqagDJFe5C1mHsKPsH8jTRHIn9lXEqjb3NXc4s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HKTrD/8e4ieDlRfD422Zuyx+D3R2Sr5c3Akg5YBKTwRdTC0YgbDNZi4nkH8jw2U5m8jxDWTMJXv2a1cjyN5/zeL8zzmE4XLeSMcI/tNLlZf7oxtpOFypAkTjR+WXqX19mtXJEEjzq2Y9ew3behUhhnRp+BvlFqsV3LSgechUkiY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ePvbCZ9/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ePvbCZ9/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8BEA5C4CECF; Thu, 17 Oct 2024 01:59:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729130352; bh=tNqaONqagDJFe5C1mHsKPsH8jTRHIn9lXEqjb3NXc4s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ePvbCZ9/+8mHCocUfsTKlLtsQCMNhpCkuYmxm3c5v1G2ZkYbU5ZxEpleH3W1lIehI dFpHob6h8M881fvRpJwac74QHRopu2ZSLACovBRLo2GBzgTnhlYJ/wrr1GlhJ4MOrQ zawwFknY2WxXz5ccQmBWs4UIwfxQzBDhW+cj2TGQg5OOhqfJ9o+tLC0ba6qtZLPgqj +jk3MIR86xMBqY7EYwAzjXZhMWH/TVD6fJRx6jt6n/gJ5uwk37ZX+3ThkGHWtHEDfw xBktD83JOquLzVXDsnxxUQWudTjIhGKqTn0nnRSYPj4Ng5yU9TQ56q4pWC2rCXEN0w nHGHf7a4DgaUw== From: Damien Le Moal To: Manivannan Sadhasivam , Lorenzo Pieralisi , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , linux-pci@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , devicetree@vger.kernel.org Cc: linux-rockchip@lists.infradead.org, Rick Wertenbroek , Niklas Cassel Subject: [PATCH v5 10/14] PCI: rockchip-ep: Refactor endpoint link training enable Date: Thu, 17 Oct 2024 10:58:45 +0900 Message-ID: <20241017015849.190271-11-dlemoal@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241017015849.190271-1-dlemoal@kernel.org> References: <20241017015849.190271-1-dlemoal@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The function rockchip_pcie_init_port() enables link training for a controller configured in EP mode. Enabling link training is again done in rockchip_pcie_ep_probe() after that function executed rockchip_pcie_init_port(). Enabling link training only needs to be done once, and doing so at the probe stage before the controller is actually started by the user serves no purpose. Refactor this by removing the link training enablement from both rockchip_pcie_init_port() and rockchip_pcie_ep_probe() and moving it to the endpoint start operation defined with rockchip_pcie_ep_start(). Enabling the controller configuration using the PCIE_CLIENT_CONF_ENABLE bit in the same PCIE_CLIENT_CONFIG register is also moved to rockchip_pcie_ep_start() and both the controller configuration and link training enable bits are set with a single call to rockchip_pcie_write(). Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 13 ++++++------- drivers/pci/controller/pcie-rockchip.c | 5 +++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index d980e0b92745..256a90485fe4 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -464,6 +464,12 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc) rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG); + /* Enable configuration and start link training */ + rockchip_pcie_write(rockchip, + PCIE_CLIENT_LINK_TRAIN_ENABLE | + PCIE_CLIENT_CONF_ENABLE, + PCIE_CLIENT_CONFIG); + return 0; } @@ -653,16 +659,9 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) rockchip_pcie_ep_hide_broken_msix_cap(rockchip); - /* Establish the link automatically */ - rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, - PCIE_CLIENT_CONFIG); - /* Only enable function 0 by default */ rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); - rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, - PCIE_CLIENT_CONFIG); - pci_epc_init_notify(epc); return 0; diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index c07d7129f1c7..154e78819e6e 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -244,11 +244,12 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, PCIE_CLIENT_CONFIG); - regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | + regs = PCIE_CLIENT_ARI_ENABLE | PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); if (rockchip->is_rc) - regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; + regs |= PCIE_CLIENT_LINK_TRAIN_ENABLE | + PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; else regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP;