From patchwork Mon Nov 18 08:04:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13878234 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 097A113DDDF; Mon, 18 Nov 2024 08:05:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731917136; cv=none; b=e3+aLoIij8j7b1LIR/VM5OxfRRZ2Z/skLxms4tew5VAwasa0shljNAjzwtZ2sBuW/aJX7i08hMMtAzHenz9MeS9VeWr8r4n528BUrDjkvj2epv1S6N+aV6kezzvTOr1/k6PX1908SJW2FHMfxbqJEaR4IgnXrnb+S3968MUb/6o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731917136; c=relaxed/simple; bh=DhSJnQhwThCB5J0umXx/t8RzQXQNejO05g1shMYhbU4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Tsi7la1aovCILvIXo+7PpluB5+esRfoUB7qWcE/xp5vFyoBPjUb8yHhU2ohm9Hi3yKam62oObW6+w/SR7kpyEnMApHDWVPYTA5i6yTLbtjA0U7n/n5Hasbo/cX8wMhajVJATsTbCAwT4S+Xi5GUrC4DgPcjSfbwvJO73ecdl/2I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e6hpPiY3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e6hpPiY3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 35667C4CECC; Mon, 18 Nov 2024 08:05:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731917135; bh=DhSJnQhwThCB5J0umXx/t8RzQXQNejO05g1shMYhbU4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=e6hpPiY3kW6xbiu60te+uoUxs/sfDCh7sWjP/NPeEdoYRpNa1+/JPOjoeCEo202xu Y8C0gLgoGDfoi5hhxlX5h1LPgaS8KKpXN9cMhe+YyOp7bv0761UPhfMM4X2avsr67i h8nFkhJO4yXDhTi1g0uZwaeuiaE000y9qVLfEOhwc8KMREy+pzDfPe5qH8s0h1IEzb 87gkAnyl7wn+IjPYxg0NO0mNXRLOnc5Kb0tZZeIrAxnl8HbAH2JemtZc0IFPEkpYmu R/MGJASMi4lY8jHZtPjJvhiDcFzPs4zDYBXKaL0I8k0ZZUfcNqd4810ggZdK3pehoK k0/7BXsz+CBQA== From: Lorenzo Bianconi Date: Mon, 18 Nov 2024 09:04:57 +0100 Subject: [PATCH v4 5/6] PCI: mediatek-gen3: Add reset delay in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241118-pcie-en7581-fixes-v4-5-24bb61703ad7@kernel.org> References: <20241118-pcie-en7581-fixes-v4-0-24bb61703ad7@kernel.org> In-Reply-To: <20241118-pcie-en7581-fixes-v4-0-24bb61703ad7@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal causing occasional PCIe link down issues. In order to overcome the problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and REG_RESET_CONTROL (0x834) registers available in the clock module running clk_bulk_prepare_enable in mtk_pcie_en7581_power_up(). In order to make the code more readable, move the wait for the time needed to complete the PCIe reset from en7581_pci_enable() to mtk_pcie_en7581_power_up(). Reduce reset timeout from 250ms to PCIE_T_PVPERL_MS (100ms). Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Lorenzo Bianconi Acked-by: Stephen Boyd --- drivers/clk/clk-en7523.c | 1 - drivers/pci/controller/pcie-mediatek-gen3.c | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 22fbea61c3dcc05e63f8fa37e203c62b2a6fe79e..bf9d9594bef8a54316e28e56a1642ecb0562377a 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -393,7 +393,6 @@ static int en7581_pci_enable(struct clk_hw *hw) REG_PCI_CONTROL_PERSTOUT; val = readl(np_base + REG_PCI_CONTROL); writel(val | mask, np_base + REG_PCI_CONTROL); - msleep(250); return 0; } diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index e4f890a73cb8ada7423301fa7a9acc3e177d0cad..f47c0f2995d94ea99bf41146657bd90b87781a7c 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -980,6 +980,13 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) goto err_clk_prepare_enable; } + /* + * Airoha EN7581 performs PCIe reset via clk callabacks since it has a + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to + * complete the PCIe reset. + */ + msleep(PCIE_T_PVPERL_MS); + return 0; err_clk_prepare_enable: