From patchwork Tue Nov 26 15:51:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Bruel X-Patchwork-Id: 13886120 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9882C1D89F7; Tue, 26 Nov 2024 15:55:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732636519; cv=none; b=imRAYeinHR4Km8Y4tzIqeLP1JTFARmFt5VWod+rA7JgjCHv1PibWjjSwAVhDnZD+HmOCKnkt1kpKQblTqByP/6SfxD5GEggw1ZBrxqUxTC8YnF2j6XFyEVXEeibhZMgUwDVTdRal/BFjeVIDrhkQKK6xboro8Wwyz2egpgwl1s8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732636519; c=relaxed/simple; bh=fe4DB9Z7QiZLM+Fb94CTtjjzbVrDS5pB9yCpgwMJ8oU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g5i1cCkFZvOexUVnKJhdAzr0aBtIJcsD2xm7ZDDL25VQY3psJ+GOHloaAm8KH7nJ84GZDxYG+09QpzHTcU6BHv/y6R0if0TD45Pw3heVEym6f29MClzQKoN8/13XCrDlEWSbkEelpKGDAuHqPcJU96nXsRhurtrPUwhKDLejNR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=BUBdaeIw; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="BUBdaeIw" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AQAkAEJ029955; Tue, 26 Nov 2024 16:54:52 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= dEFqpwvFBOahKBFYGzVlW8NZlc8J7PjUaETqIykE3YI=; b=BUBdaeIwopyrZ7zE wl8a/P7SdOXP40QRJ+GNX13wz9A8Mug9vJTp9XffqoOhIgJMnx5RnxnpHRAG8vMQ ZS7DOX3HBSahg0TvoEZumhSgnW4n+iQh6uFfYsuNh3JAZ2b3PnB0K+YaQk9OkDAS BTsfUMNXVwejC93OlsNwqyDkf5ZMeLyE9Daz03tFPC0oHfi/RtZP47nYDnWoKGdt 8wzdPMXBT1FIz3if/Gqjb8sPKNd8UwNDj+9S/zanZojHaRgxhoMhc3kvWXcucao0 zqxffj21F+WT51NIaRgFAZ7tz6lWOKZXfTa2Pvo7C7tDzHwqv255aSawSerxgJxZ QH/qtg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 433791ww76-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Nov 2024 16:54:52 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 8006340049; Tue, 26 Nov 2024 16:53:26 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3243129DE93; Tue, 26 Nov 2024 16:51:37 +0100 (CET) Received: from localhost (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 26 Nov 2024 16:51:36 +0100 From: Christian Bruel To: , , , , , , , , , , , , CC: , , , , , Christian Bruel Subject: [PATCH v2 1/5] dt-bindings: PCI: Add STM32MP25 PCIe root complex bindings Date: Tue, 26 Nov 2024 16:51:15 +0100 Message-ID: <20241126155119.1574564-2-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241126155119.1574564-1-christian.bruel@foss.st.com> References: <20241126155119.1574564-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Document the bindings for STM32MP25 PCIe Controller configured in root complex mode. Supports 4 legacy interrupts and MSI interrupts from the ARM GICv2m controller. STM32 PCIe may be in a power domain which is the case for the STM32MP25 based boards. Supports wake# from wake-gpios Signed-off-by: Christian Bruel --- .../bindings/pci/st,stm32-pcie-common.yaml | 45 +++++++++ .../bindings/pci/st,stm32-pcie-host.yaml | 99 +++++++++++++++++++ 2 files changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml new file mode 100644 index 000000000000..479c03134da3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32MP25 PCIe RC/EP controller + +maintainers: + - Christian Bruel + +description: + STM32MP25 PCIe RC/EP common properties + +properties: + clocks: + maxItems: 1 + description: PCIe system clock + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + power-domains: + maxItems: 1 + + access-controllers: + maxItems: 1 + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + +required: + - clocks + - resets + - phys + - phy-names + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml new file mode 100644 index 000000000000..18083cc69024 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32MP25 PCIe root complex driver + +maintainers: + - Christian Bruel + +description: + PCIe root complex controller based on the Synopsys DesignWare PCIe core. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# + +select: + properties: + compatible: + const: st,stm32mp25-pcie-rc + required: + - compatible + +properties: + compatible: + const: st,stm32mp25-pcie-rc + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: config + + num-lanes: + const: 1 + + msi-parent: + maxItems: 1 + + wake-gpios: + description: GPIO controlled connection to WAKE# input signal + maxItems: 1 + + wakeup-source: true + +dependentRequired: + wakeup-source: [ wake-gpios ] + +required: + - interrupt-map + - interrupt-map-mask + - ranges + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + pcie@48400000 { + compatible = "st,stm32mp25-pcie-rc"; + device_type = "pci"; + num-lanes = <1>; + reg = <0x48400000 0x400000>, + <0x10000000 0x10000>; + reg-names = "dbi", "config"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0 0x10010000 0x10010000 0 0x10000>, + <0x02000000 0 0x10020000 0x10020000 0 0x7fe0000>, + <0x42000000 0 0x18000000 0x18000000 0 0x8000000>; + clocks = <&rcc CK_BUS_PCIE>; + phys = <&combophy PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + resets = <&rcc PCIE_R>; + msi-parent = <&v2m0>; + wakeup-source; + wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + }; +