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client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by MWH0EPF000A6732.mail.protection.outlook.com (10.167.249.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8207.12 via Frontend Transport; Wed, 27 Nov 2024 11:58:30 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 27 Nov 2024 05:58:29 -0600 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Wed, 27 Nov 2024 05:58:25 -0600 From: Thippeswamy Havalige To: , , , , , , CC: , , , , , , Thippeswamy Havalige Subject: [PATCH 1/2] dt-bindings: PCI: amd-mdb: Add YAML schemas for AMD Versal2 MDB PCIe Root Port Bridge Date: Wed, 27 Nov 2024 17:28:03 +0530 Message-ID: <20241127115804.2046576-2-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241127115804.2046576-1-thippeswamy.havalige@amd.com> References: <20241127115804.2046576-1-thippeswamy.havalige@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: thippeswamy.havalige@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6732:EE_|PH0PR12MB7789:EE_ X-MS-Office365-Filtering-Correlation-Id: d99d1c63-97a8-4e59-9be6-08dd0edacfa5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|7416014|82310400026; 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Signed-off-by: Thippeswamy Havalige --- .../devicetree/bindings/pci/amd,mdb-pcie.yaml | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amd,mdb-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/amd,mdb-pcie.yaml b/Documentation/devicetree/bindings/pci/amd,mdb-pcie.yaml new file mode 100644 index 000000000000..ad9e447e87f2 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/amd,mdb-pcie.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/amd,mdb-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD versal2 MDB(Multimedia DMA Bridge) Host Controller device tree + +maintainers: + - Thippeswamy Havalige + +properties: + compatible: + const: amd,versal2-mdb-host + + reg: + items: + - description: MDB PCIe controller 0 SLCR + - description: configuration region + - description: data bus interface + - description: address translation unit register + + reg-names: + items: + - const: mdb_pcie_slcr + - const: config + - const: dbi + - const: atu + + ranges: + maxItems: 2 + + msi-map: + maxItems: 1 + + bus-range: + maxItems: 1 + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + device_type: + const: pci + + interrupts: + maxItems: 1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling legacy PCI interrupts. + type: object + properties: + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + required: + - interrupt-controller + - "#address-cells" + - "#interrupt-cells" + + additionalProperties: false + +required: + - reg + - reg-names + - interrupts + - interrupt-map + - interrupt-map-mask + - msi-map + - ranges + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pci@ed931000 { + compatible = "amd,versal2-mdb-host"; + reg = <0x0 0xed931000 0x0 0x2000>, + <0x1000 0x100000 0x0 0xff00000>, + <0x1000 0x0 0x0 0x100000>, + <0x0 0xed860000 0x0 0x2000>; + reg-names = "mdb_pcie_slcr", "config", "dbi", "atu"; + ranges = <0x2000000 0x00 0xa8000000 0x00 0xa8000000 0x00 0x10000000>, + <0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>; + interrupts = <0 198 4>; + interrupt-parent = <&gic>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + msi-map = <0x0 &gic_its 0x00 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + };