From patchwork Fri Jan 3 06:00:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 13925164 X-Patchwork-Delegate: kw@linux.com Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0A1A1BC085; Fri, 3 Jan 2025 06:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735884062; cv=none; b=F3G/bzvFAvd/HO9lyTpPHZBlKR/TiNPe1zDyVSHWEM/SZyHndLASr3YbC8b64clKEB8glgLTHNr4ClMBDDEc6bG4ky4aYde5374VLyZRkffW7AxdcnzXaj5Fevcs8aYfO3Wpa4r33jkzNq3Aypn6zWFGPk/dmseuB0QFhizR8U8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735884062; c=relaxed/simple; bh=4wS3D5ketIGa386i3zuuKr5g4b+lU53mHq+48TaJIwM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fgEzlQMBMd53gwuAIfcF1xnD0Fjf6ZtzeXbLPHC9wFm3KQQUDHs7qTbVM0Ea9yWTPCdrseOp/PQHfVPkVheNqHpo5eT88IsbsKNNm4F5k4SEL7seg1/RD7VDUOTml6LpUXfSoXjFPThWj8zvCAzFJ969EbszFgdU7xLGuL9QlFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=iQ0neLuW; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="iQ0neLuW" X-UUID: 132e45c6c99811ef99858b75a2457dd9-20250103 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=7fSI14JXINs/0jFNxsxkI+ZTe1Oh5xsksvQrQ5PGxns=; b=iQ0neLuW5KlMOjCVH4HYY9qWkjaRhsQHNPGgVc15Tbn/yi9sJjYwkBsQPHhcDwKQj9qOZ0MMf3Bz/VDFACFN0aA64P2rrUCq6KUuudUMKdXCXSH+aZa7AFjxIsq1k+7QxFwEBl6xJ5yOcC4PS6sdmUHlmzqKett+GE6nHH57q+A=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46,REQID:f5252748-ae6d-432c-809d-005f39d33410,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:60aa074,CLOUDID:05c34419-ec44-4348-86ee-ebcff634972b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 ,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 132e45c6c99811ef99858b75a2457dd9-20250103 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1676801721; Fri, 03 Jan 2025 14:00:46 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 3 Jan 2025 14:00:45 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 3 Jan 2025 14:00:44 +0800 From: Jianjun Wang To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Ryder Lee , Jianjun Wang , , , , , , Xavier Chang Subject: [PATCH 1/5] dt-bindings: PCI: mediatek-gen3: Add MT8196 support Date: Fri, 3 Jan 2025 14:00:11 +0800 Message-ID: <20250103060035.30688-2-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250103060035.30688-1-jianjun.wang@mediatek.com> References: <20250103060035.30688-1-jianjun.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Add compatible string and clock definition for MT8196. It has 6 clocks like the MT8195, but 2 of them are different. Signed-off-by: Jianjun Wang --- .../bindings/pci/mediatek-pcie-gen3.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index f05aab2b1add..b4158a666fb6 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -51,6 +51,7 @@ properties: - mediatek,mt7986-pcie - mediatek,mt8188-pcie - mediatek,mt8195-pcie + - mediatek,mt8196-pcie - const: mediatek,mt8192-pcie - const: mediatek,mt8192-pcie - const: airoha,en7581-pcie @@ -197,6 +198,34 @@ allOf: minItems: 1 maxItems: 2 + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8196-pcie + then: + properties: + clocks: + minItems: 6 + + clock-names: + items: + - const: pl_250m + - const: tl_26m + - const: peri_26m + - const: peri_mem + - const: ahb_apb + - const: low_power + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + - if: properties: compatible: