Message ID | 20250107143852.3692571-12-terry.bowman@amd.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Bjorn Helgaas |
Headers | show |
Series | Enable CXL PCIe port protocol error handling and logging | expand |
On Tue, 7 Jan 2025 08:38:47 -0600 Terry Bowman <terry.bowman@amd.com> wrote: > The CXL RAS handlers do not currently log if the RAS registers are > unmapped. This is needed inorder to help debug CXL error handling. Update > the CXL driver to log a warning message if the RAS register block is > unmapped. > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/core/pci.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 5699ee5b29df..8275b3dc3589 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -656,8 +656,10 @@ static void __cxl_handle_cor_ras(struct device *dev, > void __iomem *addr; > u32 status; > > - if (!ras_base) > + if (!ras_base) { > + dev_warn_once(dev, "CXL RAS register block is not mapped"); > return; > + } > > addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; > status = readl(addr); > @@ -700,8 +702,10 @@ static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) > u32 status; > u32 fe; > > - if (!ras_base) > + if (!ras_base) { > + dev_warn_once(dev, "CXL RAS register block is not mapped"); > return false; > + } > > addr = ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; > status = readl(addr);
Terry Bowman wrote: > The CXL RAS handlers do not currently log if the RAS registers are > unmapped. This is needed inorder to help debug CXL error handling. Update ^^^^^^^ in order Reviewed-by: Ira Weiny <ira.weiny@intel.com> [snip]
On Tue, Jan 07, 2025 at 08:38:47AM -0600, Terry Bowman wrote: > The CXL RAS handlers do not currently log if the RAS registers are > unmapped. This is needed inorder to help debug CXL error handling. Update > the CXL driver to log a warning message if the RAS register block is > unmapped. > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net>
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 5699ee5b29df..8275b3dc3589 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -656,8 +656,10 @@ static void __cxl_handle_cor_ras(struct device *dev, void __iomem *addr; u32 status; - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return; + } addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status = readl(addr); @@ -700,8 +702,10 @@ static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) u32 status; u32 fe; - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return false; + } addr = ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status = readl(addr);
The CXL RAS handlers do not currently log if the RAS registers are unmapped. This is needed inorder to help debug CXL error handling. Update the CXL driver to log a warning message if the RAS register block is unmapped. Signed-off-by: Terry Bowman <terry.bowman@amd.com> --- drivers/cxl/core/pci.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)