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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2025 14:41:50.7746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f1bf85d-7847-4e26-14bc-08dd2f296c0b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF0000020A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6396 pci_driver::cxl_err_handlers are not currently assigned handler callbacks. The handlers can't be set in the pci_driver static definition because the CXL PCIe Port devices are bound to the portdrv driver which is not CXL driver aware. Add cxl_assign_port_error_handlers() in the cxl_core module. This function will assign the default handlers for a CXL PCIe Port device. When the CXL Port (cxl_port or cxl_dport) is destroyed the device's pci_driver::cxl_err_handlers must be set to NULL indicating they should no longer be used. Create cxl_clear_port_error_handlers() and register it to be called when the CXL Port device (cxl_port or cxl_dport) is destroyed. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 49 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 3e87fe54a1a2..9c162120f0fe 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -848,8 +848,40 @@ static bool cxl_port_error_detected(struct pci_dev *pdev) return __cxl_handle_ras(&pdev->dev, ras_base); } +static const struct cxl_error_handlers cxl_port_error_handlers = { + .error_detected = cxl_port_error_detected, + .cor_error_detected = cxl_port_cor_error_detected, +}; + +static void cxl_assign_port_error_handlers(struct pci_dev *pdev) +{ + struct pci_driver *pdrv; + + if (!pdev || !pdev->driver || !get_device(&pdev->dev)) + return; + + pdrv = pdev->driver; + pdrv->cxl_err_handler = &cxl_port_error_handlers; + put_device(&pdev->dev); +} + +static void cxl_clear_port_error_handlers(void *data) +{ + struct pci_dev *pdev = data; + struct pci_driver *pdrv; + + if (!pdev || !pdev->driver || !get_device(&pdev->dev)) + return; + + pdrv = pdev->driver; + pdrv->cxl_err_handler = NULL; + put_device(&pdev->dev); +} + void cxl_uport_init_ras_reporting(struct cxl_port *port) { + struct pci_dev *pdev = to_pci_dev(port->uport_dev); + /* uport may have more than 1 downstream EP. Check if already mapped. */ if (port->uport_regs.ras) return; @@ -860,6 +892,9 @@ void cxl_uport_init_ras_reporting(struct cxl_port *port) dev_err(&port->dev, "Failed to map RAS capability.\n"); return; } + + cxl_assign_port_error_handlers(pdev); + devm_add_action_or_reset(&port->dev, cxl_clear_port_error_handlers, pdev); } EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, "CXL"); @@ -871,6 +906,8 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) { struct device *dport_dev = dport->dport_dev; struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev); + struct pci_dev *pdev = to_pci_dev(dport_dev); + struct cxl_port *port; dport->reg_map.host = dport_dev; if (dport->rch && host_bridge->native_aer) { @@ -887,6 +924,18 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) dev_err(dport_dev, "Failed to map RAS capability.\n"); return; } + + if (dport->rch) + return; + + port = find_cxl_port(dport_dev, NULL); + if (!port) { + dev_err(dport_dev, "Failed to find upstream port\n"); + return; + } + cxl_assign_port_error_handlers(pdev); + devm_add_action_or_reset(&port->dev, cxl_clear_port_error_handlers, pdev); + put_device(&port->dev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL");