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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B06A.mail.protection.outlook.com (10.167.243.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8356.0 via Frontend Transport; Tue, 7 Jan 2025 14:39:21 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 7 Jan 2025 08:39:19 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 02/16] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe Port support Date: Tue, 7 Jan 2025 08:38:38 -0600 Message-ID: <20250107143852.3692571-3-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250107143852.3692571-1-terry.bowman@amd.com> References: <20250107143852.3692571-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06A:EE_|SA1PR12MB5658:EE_ X-MS-Office365-Filtering-Correlation-Id: ecf81551-72ae-4aa4-7b33-08dd2f2912bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024|7416014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2025 14:39:21.0400 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ecf81551-72ae-4aa4-7b33-08dd2f2912bf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06A.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5658 The AER service driver already includes support for Restricted CXL host (RCH) Downstream Port Protocol Error handling. The current implementation is based on CXL1.1 using a Root Complex Event Collector. Rename function interfaces and parameters where necessary to include virtual hierarchy (VH) mode CXL PCIe Port error handling alongside the RCH handling.[1] The CXL PCIe Port Protocol Error handling support will be added in a future patch. Limit changes to renaming variable and function names. No functional changes are added. [1] CXL 3.1 Spec, 9.12.2 CXL Virtual Hierarchy Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Fan Ni --- drivers/pci/pcie/aer.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 34ce9f834d0c..0e2478f4fca2 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1030,7 +1030,7 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) return 0; } -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) +static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) { /* * Internal errors of an RCEC indicate an AER error in an @@ -1053,30 +1053,30 @@ static int handles_cxl_error_iter(struct pci_dev *dev, void *data) return *handles_cxl; } -static bool handles_cxl_errors(struct pci_dev *rcec) +static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl = false; - if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && + pcie_aer_is_native(dev)) + pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); return handles_cxl; } -static void cxl_rch_enable_rcec(struct pci_dev *rcec) +static void cxl_enable_internal_errors(struct pci_dev *dev) { - if (!handles_cxl_errors(rcec)) + if (!handles_cxl_errors(dev)) return; - pci_aer_unmask_internal_errors(rcec); - pci_info(rcec, "CXL: Internal errors unmasked"); + pci_aer_unmask_internal_errors(dev); + pci_info(dev, "CXL: Internal errors unmasked"); } #else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } -static inline void cxl_rch_handle_error(struct pci_dev *dev, - struct aer_err_info *info) { } +static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } +static inline void cxl_handle_error(struct pci_dev *dev, + struct aer_err_info *info) { } #endif /** @@ -1114,7 +1114,7 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) { - cxl_rch_handle_error(dev, info); + cxl_handle_error(dev, info); pci_aer_handle_error(dev, info); pci_dev_put(dev); } @@ -1494,7 +1494,7 @@ static int aer_probe(struct pcie_device *dev) return status; } - cxl_rch_enable_rcec(port); + cxl_enable_internal_errors(port); aer_enable_rootport(rpc); pci_info(port, "enabled with IRQ %d\n", dev->irq); return 0;