From patchwork Tue Jan 14 17:08:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13938980 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7542714B97E; Tue, 14 Jan 2025 17:09:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736874550; cv=none; b=Yo+PYWDiRYlT9kJkcEBKYldBJJMlQYt844UqjcQ5RNSkfUIBNBEmDdU9F+iJ5WN2diZVttJzOlo/Jx8G1Jc0OAH6+GW0HxTn7cV15S/LaiHYRL7jl4tlix6FJP9r2HTn/m+KkX6HDk342k06So9GhMBc8fV1ErC10+PwXfIjnnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736874550; c=relaxed/simple; bh=Pmf0mERBbsrlwrPgn3Zx9waxXdXa/Lnwkdukhw5FyGU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=r4/00INyluP5hYBlmDbQxYA9PnOGiKySw2AzgB1nKJkqXgk+RGHABOf5MNZnrobmGVWqhOKXSTkq/Kz9ahCrCDShWByEywzuNGBVTzYo8fGAc6L1EOF2styV1LE1Bx8WgdBqiP5MAuNnxXWC81Iz0epzPfQpTWHNp1zTRn6I90w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bILPeAIc; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bILPeAIc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736874549; x=1768410549; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Pmf0mERBbsrlwrPgn3Zx9waxXdXa/Lnwkdukhw5FyGU=; b=bILPeAIc9WPHszD4vbBgfnuvcpXA+gPEHtQHRBrSyZy5NrTwhCnkx6K6 ocyxAZ5i6DlHB7+USqVhlLkg54jYTVduQiq1Nu95fsPybMyMIfm+8WVdR 6LEGbT3LQl4OzM5PFjnhae5g1bVJrV5n5UWT8p7u4Hgo6laD0Xhs6noe1 melzdbGX+lcE5ig3oFXznbKW00gEXqRKSn0b2ccRc4QRaGeSMAJ71fTdZ 5uu4bxhkYcLjiBqRFmgEEESNAJ6qLQTiD+4hiJRIYSkX5blT9eoIAPxu6 Uau7fwhZyyV9nc2fglrFyLlrFz2zLMmPdl+RPWUK4znWdt2za7gOSKELh A==; X-CSE-ConnectionGUID: 73WViANuShuW1TzUPKo1AA== X-CSE-MsgGUID: 5tIgMjvgTpydgpLJCaaWcw== X-IronPort-AV: E=McAfee;i="6700,10204,11315"; a="24783708" X-IronPort-AV: E=Sophos;i="6.12,314,1728975600"; d="scan'208";a="24783708" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2025 09:09:07 -0800 X-CSE-ConnectionGUID: FeOh3efjTNuYocifUlK5ew== X-CSE-MsgGUID: KrVasvItSVu9A7VOJ8XS7w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,314,1728975600"; d="scan'208";a="105377303" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.54]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2025 09:09:04 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, Yazen Ghannam , Jonathan Cameron , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Lukas Wunner , Mahesh J Salgaonkar , Oliver O'Halloran , linux-kernel@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v9 2/8] PCI: Move TLP Log handling to own file Date: Tue, 14 Jan 2025 19:08:34 +0200 Message-Id: <20250114170840.1633-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250114170840.1633-1-ilpo.jarvinen@linux.intel.com> References: <20250114170840.1633-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 TLP Log is PCIe feature and is processed only by AER and DPC. Configwise, DPC depends AER being enabled. In lack of better place, the TLP Log handling code was initially placed into pci.c but it can be easily placed in a separate file. Move TLP Log handling code to own file under pcie/ subdirectory and include it only when AER is enabled. Signed-off-by: Ilpo Järvinen Reviewed-by: Jonathan Cameron Reviewed-by: Yazen Ghannam --- drivers/pci/pci.c | 27 --------------------------- drivers/pci/pci.h | 2 +- drivers/pci/pcie/Makefile | 2 +- drivers/pci/pcie/tlp.c | 39 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 41 insertions(+), 29 deletions(-) create mode 100644 drivers/pci/pcie/tlp.c diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e0fdc9d10f91..02cd4c7eb80b 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1099,33 +1099,6 @@ static void pci_enable_acs(struct pci_dev *dev) pci_write_config_word(dev, pos + PCI_ACS_CTRL, caps.ctrl); } -/** - * pcie_read_tlp_log - read TLP Header Log - * @dev: PCIe device - * @where: PCI Config offset of TLP Header Log - * @tlp_log: TLP Log structure to fill - * - * Fill @tlp_log from TLP Header Log registers, e.g., AER or DPC. - * - * Return: 0 on success and filled TLP Log structure, <0 on error. - */ -int pcie_read_tlp_log(struct pci_dev *dev, int where, - struct pcie_tlp_log *tlp_log) -{ - int i, ret; - - memset(tlp_log, 0, sizeof(*tlp_log)); - - for (i = 0; i < 4; i++) { - ret = pci_read_config_dword(dev, where + i * 4, - &tlp_log->dw[i]); - if (ret) - return pcibios_err_to_errno(ret); - } - - return 0; -} - /** * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) * @dev: PCI device to have its BARs restored diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 8a60fc9e7786..55fcf3bac4f7 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -549,9 +549,9 @@ struct aer_err_info { int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); -#endif /* CONFIG_PCIEAER */ int pcie_read_tlp_log(struct pci_dev *dev, int where, struct pcie_tlp_log *log); +#endif /* CONFIG_PCIEAER */ #ifdef CONFIG_PCIEPORTBUS /* Cached RCEC Endpoint Association */ diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 53ccab62314d..173829aa02e6 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -7,7 +7,7 @@ pcieportdrv-y := portdrv.o rcec.o obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o bwctrl.o obj-y += aspm.o -obj-$(CONFIG_PCIEAER) += aer.o err.o +obj-$(CONFIG_PCIEAER) += aer.o err.o tlp.o obj-$(CONFIG_PCIEAER_INJECT) += aer_inject.o obj-$(CONFIG_PCIE_PME) += pme.o obj-$(CONFIG_PCIE_DPC) += dpc.o diff --git a/drivers/pci/pcie/tlp.c b/drivers/pci/pcie/tlp.c new file mode 100644 index 000000000000..3f053cc62290 --- /dev/null +++ b/drivers/pci/pcie/tlp.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe TLP Log handling + * + * Copyright (C) 2024 Intel Corporation + */ + +#include +#include +#include + +#include "../pci.h" + +/** + * pcie_read_tlp_log - read TLP Header Log + * @dev: PCIe device + * @where: PCI Config offset of TLP Header Log + * @tlp_log: TLP Log structure to fill + * + * Fill @tlp_log from TLP Header Log registers, e.g., AER or DPC. + * + * Return: 0 on success and filled TLP Log structure, <0 on error. + */ +int pcie_read_tlp_log(struct pci_dev *dev, int where, + struct pcie_tlp_log *tlp_log) +{ + int i, ret; + + memset(tlp_log, 0, sizeof(*tlp_log)); + + for (i = 0; i < 4; i++) { + ret = pci_read_config_dword(dev, where + i * 4, + &tlp_log->dw[i]); + if (ret) + return pcibios_err_to_errno(ret); + } + + return 0; +}