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Tue, 28 Jan 2025 13:11:29 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id F2AD22A27AB; Tue, 28 Jan 2025 13:09:44 +0100 (CET) Received: from localhost (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 28 Jan 2025 13:09:44 +0100 From: Christian Bruel To: , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v4 09/10] arm64: dts: st: Add PCIe Endpoint mode on stm32mp251 Date: Tue, 28 Jan 2025 13:07:44 +0100 Message-ID: <20250128120745.334377-10-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250128120745.334377-1-christian.bruel@foss.st.com> References: <20250128120745.334377-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-28_04,2025-01-27_01,2024-11-22_01 Add pcie_ep node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Endpoint mode Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 6cd1a765fac9..07c2d2c386f4 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -909,6 +909,19 @@ stmmac_axi_config_1: stmmac-axi-config { }; }; + pcie_ep: pcie-ep@48400000 { + compatible = "st,stm32mp25-pcie-ep"; + reg = <0x48400000 0x400000>, + <0x10000000 0x8000000>; + reg-names = "dbi", "addr_space"; + clocks = <&rcc CK_BUS_PCIE>; + resets = <&rcc PCIE_R>; + phys = <&combophy PHY_TYPE_PCIE>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + status = "disabled"; + }; + pcie_rc: pcie@48400000 { compatible = "st,stm32mp25-pcie-rc"; device_type = "pci"; @@ -931,6 +944,7 @@ pcie_rc: pcie@48400000 { resets = <&rcc PCIE_R>; msi-parent = <&v2m0>; access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; status = "disabled"; pcie@0,0 { @@ -942,6 +956,8 @@ pcie@0,0 { ranges; }; }; + + }; bsec: efuse@44000000 {