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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2025 12:44:13.9823 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bb03b16-39a8-4391-edd7-08dd56634687 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE16.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6840 Add GPIO-based control for the PCIe Root Port PERST# signal. According to section 2.2 of the PCIe Electromechanical Specification (Revision 6.0), PERST# signal has to be deasserted after a delay of 100 ms (TPVPERL) to ensure proper reset sequencing during PCIe initialization. Adapt to use the GPIO framework and make reset optional to keep DTB backward compatibility. Signed-off-by: Sai Krishna Musham --- This patch depends on the following patch series. https://lore.kernel.org/all/20250217072713.635643-3-thippeswamy.havalige@amd.com/ Changes for v2: - Make the request GPIO optional. - Correct the reset sequence as per PERST# - Update commit message --- drivers/pci/controller/pcie-xilinx-cpm.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index 81e8bfae53d0..aa0c61d30049 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -6,6 +6,8 @@ */ #include +#include +#include #include #include #include @@ -568,8 +570,29 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct pci_host_bridge *bridge; struct resource_entry *bus; + struct gpio_desc *reset_gpio; int err; + /* Request the GPIO for PCIe reset signal */ + reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(reset_gpio)) { + dev_err(dev, "Failed to request reset GPIO\n"); + return PTR_ERR(reset_gpio); + } + + /* Assert the reset signal */ + gpiod_set_value(reset_gpio, 1); + + /* + * As per section 2.2 of the PCI Express Card Electromechanical + * Specification (Revision 6.0), the deassertion of the PERST# signal + * should be delayed by 100 ms (TPVPERL). + */ + msleep(100); + + /* Deassert the reset signal */ + gpiod_set_value(reset_gpio, 0); + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port)); if (!bridge) return -ENODEV;